• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.101-109
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• 2017

This paper presents a high-throughput low-complexity 512-point eight-parallel mixed-radix multipath delay feedback (MDF) fast Fourier transform (FFT) processor architecture for orthogonal frequency division multiplexing (OFDM) applications. To decrease the number of twiddle factor (TF) multiplications, a mixed-radix $2^4/2^3$ FFT algorithm is adopted. Moreover, a dual-path shared canonical signed digit (CSD) complex constant multiplier using a multi-layer scheme is proposed for reducing the hardware complexity of the TF multiplication. The proposed FFT processor is implemented using TSMC 90-nm CMOS technology. The synthesis results demonstrate that the proposed FFT processor can lead to a 16% reduction in hardware complexity and higher throughput compared to conventional architectures.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.113-116
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• 2002

This paper describes a design of 8192-Point pipelined FFT/IFFT processor (PFFTSk) core for DVB-T and DMT-based VBSL modems. A novel two-step convergent block floating -point (75_CBFP) scaling method is proposed to improve the signal- to-quantization-noise ratio (SeNR) of FFT/IFFT results. Our approach reduces about 80% of memory when compared with conventional CBFP methods. The PFFTSk core, which is designed in VHDL and synthesized using 0.25-${\mu}{\textrm}{m}$ CMOS library, has about 76,300 gates, 390k bits RAM, and Twiddle factor ROM of 39k bits. Simulation results show that it can safely operate up to 50-MHz clock frequency at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-$mutextrm{s}$. The SQNR of about 60-dB is achieved.

• Proceedings of the IEEK Conference
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• 2003.11a
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• pp.473-476
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• 2003

We suggest 2 dimensional Fast Fourier Transform using Polynomial Transform and integer Fast Fourier Transform. Unlike conventional 2D-FFT using the direct quantization of twiddle factor, the suggested 2D-FFT adopts implemented by the lifting so that the suggested 2D-FFT is power adaptable and reversible. Since the suggested FFT performg integer-to-integer mapping, the transform can be implemented by only bit shifts and auditions without multiplications. In addition. polynomial transform severely reduces the multiplications of 2D-FFT. While preserving the reversibility, complexity of this algorithm is shown to be much lower than that of any other algorithms in terms of the numbers of additions and shifts.

• Proceedings of the KIPE Conference
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• 2002.07a
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• pp.657-660
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• 2002

In this paper, the FFT processor for power measurement using VHDL (Very high-speed integrated circuit Hardware Description Language) is discussed. The proposed system relies on the FFT algorithm to compute real and reactive power. The advantage of system is that harmonic analysis is carried out on a period of the Input signal. The proposed system is based on FFT Processor which is designed using VHDL. In the design of FFT processor, $radix-2^2$ is adopted to reduce several complex multipliers for twiddle factor. And this processor adopt pipeline structure. Therefore, the system Is able to have both high hardware efficiency and high performance.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.3
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• pp.191-193
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• 2005

This paper proposes a phase measurement algorithm which is based on the recursive implementation of sliding-DFT. The proposed algorithm is designed to have a robust behavior against the erroneous factors of frequency drift, additive noise, and twiddle factor approximation. Four channel power-line phase measurement system is also designed and implemented based on the time-multiplexed sharing architecture of the proposed algorithm. The proposed algorithm's features of phase measurement accuracy and its robustness against the finite wordlength effects can provide a significant impact especially for the ASIC or microprocessor based embedded system applications where the enhanced processing speed and implementation simplicity are crucial design considerations.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.13-14
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• 2006

In this paper, an efficient butterfly structure for Radix-4 FFT algorithm using DA(Distributed Arithmetic) is proposed. It is shown that DA can be efficiently used in twiddle factor calculation of the Radix-4 FFT algorithm. The Verilog-HDL coding results for the proposed DA butterfly structure show 61.02% cell area reduction comparison with those of the conventional multiplier butterfly structure. Furthermore, the 64-point Radix-4 pipeline structure using the proposed butterfly and delay commutators is compared with other conventional structures. Implementation coding results show 46.1% cell area reduction.

• Aerospace Engineering and Technology
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• v.9 no.1
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• pp.98-105
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• 2010

Fast Fourier Transform is the fast implementation of Discrete Fourier Transform, which deletes periodic operation of DFT. According to the definition, radix-2 FFT can be implemented byre cursive call which divides the input signal points into 2 signal points. Because of its time-consuming stack-copy operation, this recursive method is very slow. To overcome this drawback, butterfly operation with signal rearrangement was devised. Based on the ideas of signal rearrangement and butterfly operation, this paper applies the signal rearrangement method to the Radix-3 FFT and checks the validity of this method.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.06a
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• pp.179-183
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• 2007

This paper is to implement a low power frequency Shift Keying(FSK) receiver using Xilinx System Generator. The receiver incorporates a 16 point Fast Fourier Transform(FFT) for symbol detection. The design units of the receiver are digital designs for better efficiency and reliability. The receiver functions on one bit data processing and supports data rates 10kbps. In addition CORDIC algorithm is used for avoiding complex multiplications while computing FFT, multiplication of twiddle factor is substituted by rotators. The design and simulation of the receiver is carried out in Simulink, then the simulink model is translated to a hardware model to implement FPGA using Xilinx System Generator and to verify performance.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.8
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• pp.1488-1494
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• 2008

This paper is to design and implement a low power noncoherent BFSK receiver intended for future deep space communication using Xilinx System generator. The receiver incorporates a 16 point Fast Fourier Transform(FFT) for symbol detection. The design units of the receiver are digital design for better efficiency and reliability. The receiver functions on one bit data processing and supports main data rate 10kbps. In addition CORDIC algorithm is used for avoiding complex multiplications while computing FFT and multiplication of twiddle factor for low power is substituted by rotators. The design and simulation of the receiver is carried out in Simulink then the Simulink model is translated to the hardware model to implement FPGA using Xilinx System Generator and to verify performance.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.3
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• pp.75-81
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• 2015

This paper proposed the new eight-parallel MDC FFT processor using the eight-parallel MDC architecture and the efficient scheduling scheme. The proposed FFT processor supports the 256-point FFT based on the modified radix-$2^6$ FFT algorithm. The proposed scheduling scheme can reduce the number of complex multipliers from eight to six without increasing delay buffers and computation cycles. Moreover, the proposed FFT processor can be used in OFDM systems required high throughput and low hardware complexity. The proposed FFT processor has been designed and implemented with a 90nm CMOS technology. The experimental result shows that the area of the proposed FFT processor is $0.27mm^2$. Furthermore, the proposed eight-parallel MDC FFT processor can achieve the throughput rate up to 2.7 GSample/s at 388MHz.