• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.5
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• pp.689-695
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• 2002

Film compositions are needed in semiconductor manufacturing for such diverse application as production tool qualifications and process development. Surface and interface information is generally provided with Auger electron spectroscopy(AES). In this paper, WSix films were analyzed for structural, electrical, and compositional properties of tungsten silicide thin films produced by low pressure chemical vapor deposition as a function of temperature, DCS post flow, shower head life time, and the silicon to tungsten ratios have been investigated. We find that Si/W composition ratio is increased in the surface and interface of WSix thin films by the DCS post flow process and increasing deposition temperature, respectively. The results obtained in this study are also applicable to process control of WSix deposition for memory device fabrication.

• Journal of the Korean institute of surface engineering
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• v.30 no.6
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• pp.374-381
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• 1997

We have studied the effect of the interface between tungsten silicide and polysilicon the silicide reaction. The results showed that the cleaning of the silicon surface prior to the deposition of tungsten silicide affected the interface properties, thereby leading to the difference in the resistivity and surface morhpology of tungsten silicide. Compared with HF cleaning, the use of SCl cleaning yielded higher resistivity of tungsten silicide at the low anneal temperature (up to $900^{\circ}C$). However, furtherature to $1000^{\circ}C$ reduced the resistivity significantly, similar to that obtained with HF cleaning. It was also observed that the annealing of WSix/HF-cleaned poly-si allowed the formation of bucking weve (partially decohesion area) on the surface. In contrast, the use of SCl celaning did not produce the buckling waves on the surface. Also the presence of 200$\AA$ -thick TiW between tungsten silicide and HF-cleaned poly-Si effectively prevented the formation of the waves. However, high-temperature annealing of WSix/200A-TiW/Poly-Si allowed the excess silicon in tungsten silicide to precipitate inside the silcide, causing the slight increase of the resistivity after annealing at $1050^{\circ}C$.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.9
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• pp.15-19
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• 1992

Tungsten silicied (WSix) has been widely used for interconnection line to improve the speed and reliability of devices. It is known that WSix formed by silane reduction has poor step coverage and poor adhesion. In this research, WSix by dichlorosilane reduction showed excellent adhesion in cellophane adhesive tape test, and improved step coverage by two times. The crystal structure of the as-deposited WSix film by silane reduction was transformed from the hexagonal to the tetragonal structure during annealing treatment, while that by dichlorosilane reduction kept the stable tetragonal structure. The fluorine concentration in the WSix film by dichlorosilane was lower than that by silane.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.41-45
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• 2012

We observed that in chemical vapor deposition (CVD) tungsten silicide (WSix) poly gate scheme, the gate oxide thickness decreases as gate length is reduced, and it intensifies the roll-off properties of transistor. This is because the fluorine diffuses laterally from WSix to the gate sidewall oxide in addition to its vertical diffusion to the gate oxide during gate re-oxidation process. When the channel length is very small, the gate oxide thickness is further reduced due to a relative increase of the lateral diffusion than the vertical diffusion. In DRAM cells where the channel length is extremely small, we found the thinned gate oxide is a main cause of poor retention time.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1988.05a
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• pp.52-55
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• 1988

Tunsten silicide (WSix) films on polycrystalline silicon were formed by low-pressure chemical vapor deposition (LPCVD) and were annealed in $N_2$ for 30 mins at various temperatures. The annealing behaviors of tungsten silicide films have been investigated by electrical resistivity measurements, X-ray diffraction methods, scanning electron microscopy (SEM) and Hall measurements. The electrical resistivity decreased almost linearly with increasing annealing temperature and reached $35{\mu}{\Omega}-cm$ at $1000^{\circ}C$ annealing. The X-ray and SEM analyses indicate that crystallization of $WSi_2$ and grain growth occurs when annealed above $1000^{\circ}C$. Excess silicon redistribution occurs considerably when annealed above $1000^{\circ}C$. By Hall measurements, the carrier type for specimens annealed at $1000^{\circ}C$ was found to be positive holes, while the carriers were electrons in the specimens that were annealed at $800^{\circ}C$.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.3
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• pp.177-184
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• 2014

In chemical vapor deposition(CVD) tungsten silicide(WSix) dual poly gate(DPG) scheme, we observed the fluorine effects on gate oxide using the electrical and physical measurements. It is found that in fluorine-rich WSix NMOS transistors, the gate thickness decreases as gate length is reduced, and it intensifies the roll-off properties of transistor. This is because the fluorine diffuses laterally from WSix to the gate sidewall oxide in addition to its vertical diffusion to the gate oxide during gate re-oxidation process. When the channel length is very small, the gate oxide thickness is further reduced due to a relative increase of the lateral diffusion than the vertical diffusion. In PMOS transistors, it is observed that boron of background dopoing in $p^+$ poly retards fluorine diffusion into the gate oxide. Thus, it is suppressed the fluorine effects on gate oxide thickness with the channel length dependency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.7
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• pp.513-519
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• 2001

We proposed Si-rich tungsten silicide (WSix) films for alternate gate electrode of deep-submicron MOSFETs. The investigation of WSix films deposited directly on SiO$_2$ indicated that the annealing of as-deposited films using a rapid thermal processor (RTP) results in low resitivity, as well as negligible fluorine (F) diffusion. Specifically, the resitivity of RTP-annealed samples at 800 $^{\circ}C$ for 3 minutes in vacuum was ~160 $\mu$$\Omega$ . cm, and the irregular growth of an extra SiO$_2$ layer due to F diffusion during annealing has not been observed. In addition, the analysis of the WSix-SiO$_2$-Si (MOS) capacitors exhibits excellent electrical characteristics.