• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권1호
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• pp.717-720
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• 2007

We fabricated the 3.5 inch QCIF AMOLED panel with ultra low temperature polycrystalline silicon TFT on the plastic substrate. To reduce the leakage current, we used the triple layered gate metal structure. To reduce the stress from inorganic dielectric layer, we applied the organic interlayer dielectric and the photoactive insulating layer. By using the interlayer dielectric as a capacitor, the mask steps are reduced up to five.

• Journal of Korean Vacuum Science & Technology
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• 제2권1호
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• pp.43-48
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• 1998

The effect of mcirostructure on the electrical properties of yttria stabilized zirconia (YSZ) was analyzed by modeling layer arrangements and mixed phase structure. The YSZ thin films were deposited by RF magnetron sputtering using 30mol% YSZ and 8 mol% YSZ targets with yttrium pellets on porous alumina substrates. The structure, composition and electricla properties of the YSZ films were investigated as functions of sputtering conditons and layer arrangements by XRD, TEM, XPS and acimpedance spectroscopy. The results showed that the triple palyered YSZ films had highermicrohardness, lower compressive stress state and higher ionic conductivity by one order than single and double layered YSZ films. However, sputtered YSZ films have low conductivity compared to YSZ pellets or doctor bladed YSZ thin plates. These results were probably due to the influence of insulating alumina substrates, impractical for most stacking geometries and inductance induced by relatively long platinum, lead wire on YSZ conductivity.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2008년도 추계학술대회 초록집
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• pp.9-10
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• 2008

Triple layers structure of $SiO_2$/ZnS:Mn/ZnS was synthesized by using ion substitution and chemical precipitation method. Each layer thickness was controlled by adjusting the concentration of manganese (II) acetate ($Mn(CH_3COO)_2$) and tetraethyl orthosilicate (TEOS). The structure and morphology of prepared phosphors were investigated by X-ray diffraction (XRD), scanning electron microscopy (SEM) and electron probe microscopic analyzer (EPMA). Photoluminescence (PL) properties of ZnS with different layer thickness and amount of Mn activator were analyzed by PL spectrometer. PL emission intensity and PL stability were analyzed for evaluating effects of Mn activator.

• 한국통신학회논문지
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• 제24권6B호
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• pp.1183-1190
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• 1999

본 논문에서는 MPEG-2 비디오 인코더를 ASIC 칩으로 구현할 때, 움직임추정기와 함께 대량의 하드웨어 영역을 차지하는 프레임메모리 인터페이스를 개선한 효율적인 구조를 제시한다. 이를 위해 비디오 인코더와 듀얼 뱅크를 가지는 외부 SDRAM 사이의 인터페이스를 효율적으로 처리할 수 있도록 메모리 맵을 구성하고 메모리 액세스 타이밍을 최적화하여 내부 메모리 크기와 인터페이스 로직을 줄였다. 본 설계에는 0.5 m, CMOS, TLM(Triple Layer Metal) 표준 셀 라이브러리가 사용되었으며, 하드웨어 설계 및 검증을 위해서 VHDL 시뮬레이터와 로직 합성툴이 사용되었고, 기능 검증을 위한 테스트 벡터 생성을 위해서, C 언어로 모델링한 하드웨어 에뮬레이터가 사용되었다. 개선된 프레임 메모리 인터페이스의 구조는 기존의 구조[2-3]에 비해 58% 정도의 면적이 감소했으며, 전체 비디오 인코더에 대해서는 24.3% 정도의 하드웨어 면적이 감소되어, 프레임메모리 인터페이스가 비디오 인코더 전체의 하드웨어 면적에 대단히 심각한 영향을 미친다는 것을 결과로 제시한다.

• 센서학회지
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• 제29권5호
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• pp.354-359
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• 2020

The high vacuum hermetic sealing technique ensures excellent performance of MEMS resonators. For the high vacuum hermetic sealing, the customization of anodic bonding equipment was conducted for the glass/Si/glass triple-stack anodic bonding process. Figure 1 presents the schematic of the MEMS resonator with triple-stack high-vacuum anodic bonding. The anodic bonding process for vacuum sealing was performed with the chamber pressure lower than 5 × 10^-6 mbar, the piston pressure of 5 kN, and the applied voltage was 1 kV. The process temperature during anodic bonding was 400 ℃. To maintain the vacuum condition of the glass cavity, a getter material, such as a titanium thin film, was deposited. The getter materials was active at the 400 ℃ during the anodic bonding process. To read out the electrical signals from the Si resonator, a vertical feed-through was applied by using through glass via (TGV) which is formed by sandblasting technique of cap glass wafer. The aluminum electrodes was conformally deposited on the via-hole structure of cap glass. The TGV process provides reliable electrical interconnection between Si resonator and aluminum electrodes on the cap glass without leakage or electrical disconnection through the TGV. The fabricated MEMS resonator with proposed vacuum packaging using three-layer anodic bonding process has resonance frequency and quality factor of about 16 kHz and more than 40,000, respectively.

• 한국축산식품학회지
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• 제27권4호
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• pp.543-547
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• 2007

본 연구에서는 원유와 사일리지, 전통발효식품 등으로부터 유방염 원인균에 대한 항균성을 가지는 유산균을 분리하였고, 이들 중 원유에서는 79, 91-3 균주와 전통발효식품에서는 SA131, NK24, NK34, 32, 44-1 균주, 사일리지에서는 253, 261, 262, 263, 265 균주, 닭분변에서 B32, C23 균주에서 유방염 원인균에 대한 비교적 높은 항균력을 확인할 수 있었다. 이를 통해 새로운 항생제 대체물질의 가능성을 확인할 수 있었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권2호
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• pp.117-123
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• 2004

A 30 nm $In_{0.7}GaAs$ High Electron Mobility Transistor (HEMT) with triple-gate has been successfully fabricated using the $SiO_2/SiN_x$ sidewall process and BCB planarization. The sidewall gate process was used to obtain finer lines, and the width of the initial line could be lessened to half by this process. To fill the Schottky metal effectively to a narrow gate line after applying the developed sidewall process, the sputtered tungsten (W) metal was utilized instead of conventional e-beam evaporated metal. To reduce the parasitic capacitance through dielectric layers and the gate metal resistance ($R_g$), the etchedback BCB with a low dielectric constant was used as the supporting layer of a wide gate head, which also offered extremely low Rg of 1.7 Ohm for a total gate width ($W_g$) of 2x100m. The fabricated 30nm $In_{0.7}GaAs$ HEMTs showed $V_{th}$of -0.4V, $G_{m,max}$ of 1.7S/mm, and $f_T$ of 421GHz. These results indicate that InGaAs nano-HEMT with excellent device performance could be successfully fabricated through a reproducible and damage-free sidewall process without the aid of state-of-the-art lithography equipment. We also believe that the developed process will be directly applicable to the fabrication of deep sub-50nm InGaAs HEMTs if the initial line length can be reduced to below 50nm order.

• 마이크로전자및패키징학회지
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• 제22권4호
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• pp.77-82
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• 2015

To increase the performance of solid oxide fuel cell operating at intermediate temperature ($600^{\circ}C{\sim}800^{\circ}C$), $Sm_{0.2}Ce_{0.8}O_2$ (SDC) thin layer was applied to the $La_{0.8}Sr_{0.2}Mn_{0.8}Cu_{0.2}O_3$ (LSMCu) cathode by sol-gel coating method. The SDC was employed as a diffusion barrier layer on the yttria-stabilized zirconia(YSZ) to prevent the interlayer by-product formation of $SrZrO_3$ or $La_2Zr_2O_7$. The by-products were hardly formed at the electrolyte-cathode interlayer resulting to reduce the cathode polarization resistance. Moreover, SDC thin film was coated on the cathode pore wall surface to extend the triple phase boundary (TPB) area.

• Transactions on Electrical and Electronic Materials
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• 제16권5호
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• pp.264-267
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• 2015

AlCrNO cermet films were prepared on aluminum substrates using a DC-reactive magnetron sputtering method and a water-cooled Al:Cr target. The Al₂O₃/AlCrNO (LMVF)/AlCrNO (MMVF)/AlCrNO (HMVF)/Al/substrate of the 5 multi-layers was prepared according to the Ar and (N₂ + O₂) gas-mixture rates. The Al₂O₃ of the top layer is the anti-reflection layer of triple AlCrNO (LMVF)/AlCrNO (MMVF)/AlCrNO (HMVF) layers, and an Al metal forms the infrared reflection layer. In this study, the crystallinity and surface properties of the AlCrNO thin films were estimated using X-ray diffraction (XRD) and field-emission scanning electron microscopy (FESEM), while the composition of the thin films was systematically investigated using Auger electron spectroscopy (AES). The optical properties of the wavelength spectrum were recorded using UH4150 spectrophotometry (UV-Vis-NIR) at a range of 0.3 μm to 2.5 μm.

• 한국세라믹학회지
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• 제44권12호
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• pp.727-732
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• 2007

In order to fabricate a highly performing cathode for low-temperature type solid oxide fuel cells working at below $700^{\circ}C$, electrode microstructure control and electrode polarization measurement were performed with an electronic conductor, $La_{0.8}Sr_{0.2}MnO_3$ (LSM) and a mixed conductor, $La_{0.6}Sr_{0.4}Co_{0.2}Fe_{0.8}O_3$(LSCF). For both cathode materials, when $Sm_{0.2}Ce_{0.8}O_2$ (SDC) buffer layer was formed between the cathode and yttria-stabilized zirconia (YSZ) electrolyte, interfacial reaction products were effectively prevented at the high temperature of cathode sintering and the electrode polarization was also reduced. Moreover, cathode polarization was greatly reduced by applying the SDC sol-gel coating on the cathode pore surface, which can increase triple phase boundary from the electrolyte interface to the electrode surface. For the LSCF cathode with the SDC buffer layer and modified by the SDC sol-gel coating on the cathode pore surface, the cathode resistance was as low as 0.11 ${\Omega}{\cdot}cm^2$ measured at $700^{\circ}C$ in air atmosphere.