• Journal of Electrical Engineering and Technology
• /
• v.12 no.2
• /
• pp.865-873
• /
• 2017

Converter transformer is the key equipment of high voltage direct current transmission system. The solid suspending particles originating from the process of installation and operation of converter transformer have significant influence on the insulation performance of transformer oil, especially in presence of DC component in applied voltage. Under high electric field, the particles easily lead to partial discharge and breakdown of insulating oil. This paper investigated copper particle effect on the breakdown voltage of transformer oil at combined AC and DC voltage. A simulation model with single copper particle was established to interpret the particle effect on the breakdown strength of insulating oil. The experimental and simulation results showed that the particles distort the electric field. The breakdown voltage of insulating oil contaminated with copper particle decreases with the increase of particle number, and the breakdown voltage and the logarithm of particle number approximately satisfy the linear relationship. With the increase of the DC component in applied voltage, the breakdown voltage of contaminated insulating oil decreases. The simulation results show that the particle collides with the electrode more frequently with more DC component contained in the applied voltage, which will trigger more discharge and decrease the breakdown voltage of insulating oil.

• Journal of IKEEE
• /
• v.2 no.1 s.2
• /
• pp.101-107
• /
• 1998

This paper is studied micro-defect characteristics by phosphorus 1MeV ion implantation and Rs, SRP, SIMS, XTEM for the RTA process was measured and simulated. As the dose is higher, the Rs is lower. When the dose are $1{\times}10^{13}/cm^2,\;5{\times}10^{13}/cm^2,\;1{\times}10^{14}/cm^2$, the Rp are $1.15{\mu}m,\;1.15{\mu},\;1.10{\mu}m$ respectively. As the RTA time is longer, the maximum concentration position is deeper from the surface and the concentration is lower. Before the RTA was done, we didn't observe any defect. But after the RTA process was done, we could observe the RTA process changed the micro-defects into the secondary defects. The simulation using the buried layer and connecting layer structure was performed. As results, the connecting layer had more effect than the buried layer to latch-up immune. Trigger current was more $0.6mA/{\mu}m$ and trigger voltage was 6V at dose $1{\times}10^{14}/cm^2$ and the energy 500KeV of connecting layer Lower connecting layer dose, latch-up immune characteristics was better.

• Journal of IKEEE
• /
• v.22 no.1
• /
• pp.80-86
• /
• 2018

In this paper, we propose a new PNP bipolar insertion type ESD protection circuit with improved electrical characteristics than the existing ESD protection circuits SCR and LVTSCR. The proposed circuit has 8.59V trigger voltage which is about 9V lower than that of the conventional SCR, and the parasitic PNP has one more operation and high robustness characteristics. For the practical design of the proposed ESD protection circuit, the holding voltage was increased by increasing the base length of the parasitic PNP while increasing the variable L. To verify the electrical characteristics of the proposed device, Synopsys T-CAD simulator was used.

• Proceedings of the KIEE Conference
• /
• 2008.07a
• /
• pp.2210-2211
• /
• 2008

In this paper, we investigated the quenching characteristics of a superconducting fault current limiter (SFCL) with connection of $2{\times}3$ matrixes. This SFCL consists of the trigger part to apply magnetic field and the current-limiting part to limit the fault current. When the fault occurs, the magnetic field generated in the reactor connected in parallel was applied to the two superconducting units of the current-limiting part to reduce of inhomogeneous critical current behavior between the superconducting units. The quenching behavior of a superconducting unit in the trigger part was affected by the increase of turn numbers. This is because of the difference of current distribution between the inductance of the reactors and the resistance generated in the superconducting units in trigger part. We confirmed that the voltage differences between two superconducting units of the current-limiting part were decreased. This is because of the improvement of inhomogeneous critical current behavior between the superconducting units according to the increase of external magnetic field.

• Proceedings of the IEEK Conference
• /
• 2005.11a
• /
• pp.731-734
• /
• 2005

In this study, the design of advanced LVDS(Low Voltage Differential Signaling) I/O interface circuit with new structural low triggering ESD (Electro-Static Discharge) protection circuit was investigated. Due to the differential transmission technique and low power consumption at the same time. Maximum transmission data ratio of designed LVDS transmitter was simulated to 5Gbps. And Zener Triggered SCR devices to protect the ESD phenomenon were designed. This structure reduces the trigger voltage by making the zener junction between the lateral PNP and base of lateral NPN in SCR structure. The triggering voltage was simulated to 5.8V. Finally, we performed the layout high speed I/O interface circuit with the low triggered ESD protection device in one-chip.

• Proceedings of the IEEK Conference
• /
• 2005.11a
• /
• pp.805-808
• /
• 2005

In this study, the design of advanced LVDS(Low Voltage Differential Signaling) I/O interface circuit with new structural low triggering ESD(Electro-Static Discharge) protection circuit was investigated. Due to the differential transmission technique and low power consumption at same time. maximum transmission data ratio of designed LVDS transmitter was simulated to 5Gbps, Also, the LIGCSCR(Latch-up Immune Gate Coupled SCR)was designed. It consists of PLVTSCR (P-type Low Voltage Trigger SCR), control NMOS and RC network. The triggering voltage was simulated to 3.6V. And the latch-up characteristics were improved. Finally, we performed the layout high speed I/O interlace circuit with the low triggered ESD protection device in one-chip.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.3
• /
• pp.339-344
• /
• 2014

This paper presents a novel bipolar junction transistor (BJT) based electrostatic discharge (ESD) protection device. This protection device was designed for 20V power clamps and fabricated by a process with Bipolar-CMOS-DMOS (BCD) $0.18{\mu}m$. The current-voltage characteristics of this protection device was verified by the transmission line pulse (TLP) system and the DC BV characteristic was verified by using a semiconductor parameter analyzer. From the experimental results, the proposed device has a trigger voltage of 29.1V, holding voltage of 22.4V and low on-resistance of approximately $1.6{\Omega}$. In addition, the test of ESD robustness showed that the ESD successfully passed through human body model (HBM) 8kV. In this paper, the operational mechanism of this protection device was investigated by structural analysis of the proposed device. In addition, the proposed device were obtained as stack structures and verified.

• Journal of IKEEE
• /
• v.13 no.1
• /
• pp.87-93
• /
• 2009

The paper introduces a silicon controlled rectifier (SCR)-based device with high holding voltage for ESD power clamp. The holding voltage can be increased by extending a p+ cathode to the first n-well and adding second n-well wrapping around n+ cathode. The increase of the holding voltage above the supply voltage enables latch-up immune normal operation. In this study, the proposed device has been simulated using synopsys TCAD simulator for electrical characteristic, temperature characteristic, and ESD robustness. In the simulation result, the proposed device has holding voltage of 3.6V and trigger voltage of 10.5V. And it is confirmed that the device could have holding voltage of above 4V with the size variation of extended p+ cathode and additional n-well.

• Journal of electromagnetic engineering and science
• /
• v.18 no.1
• /
• pp.20-28
• /
• 2018

The time synchronization of each sub-unit of a pulsed generator is important to generate an output high-power radio frequency (RF) signal. To obtain the time synchronization between an input RF signal fed by an external source and an electron beam produced by an electric pulse generator, the influence of different charging voltages on a delay and a rise time of the output pulse waveform in the electric pulse generator should be carefully considered. This paper aims to study the timing characteristics of the delay and the rise time as a function of different charging voltages with a peak value of less than -35 kV in the high-voltage pulse generator, including a trigger generator (TG) and a pulse-forming line (PFL). The simulation has been carried out to estimate characteristics in the time domain, in addition to their output high-voltage amplitude. Experimental results compared with those obtained by simulation indicate that the delay of the output pulses of the TG and PFL, which are made by controlling the external triggering signal with respect to different charging voltages, is getting longer as the charging voltage is increasing, and their rise times are inversely proportional to the amplitude of the charging voltage.

• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.33 no.2
• /
• pp.113-118
• /
• 2005

This paper shows a satellite battery cell voltage monitor system to make differential voltage measurements when one or both measurement points are beyond voltage range allowed by a conventional differential amplifier. This system is particularly useful for monitoring the individual cell voltage of series-connected cells that constitute a rechargeable satellite battery in which some cell voltages must be measured in the presence of high common mode voltage.