Journal of IKEEE (전기전자학회논문지)

Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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The novel SCR-based ESD Protection Device with High Holding Voltage

높은 홀딩전압을 갖는 사이리스터 기반 새로운 구조의 ESD 보호소자

  • Won, Jong-Il (Department of Electronics Engineering, Seokyeoung University) ;
  • Koo, Yong-Seo (Department of Electronics Engineering, Seokyeoung University)
  • Published : 2009.03.31
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Abstract

The paper introduces a silicon controlled rectifier (SCR)-based device with high holding voltage for ESD power clamp. The holding voltage can be increased by extending a p+ cathode to the first n-well and adding second n-well wrapping around n+ cathode. The increase of the holding voltage above the supply voltage enables latch-up immune normal operation. In this study, the proposed device has been simulated using synopsys TCAD simulator for electrical characteristic, temperature characteristic, and ESD robustness. In the simulation result, the proposed device has holding voltage of 3.6V and trigger voltage of 10.5V. And it is confirmed that the device could have holding voltage of above 4V with the size variation of extended p+ cathode and additional n-well.

본 논문에서는 높은 홀딩 전압을 갖는 사이리스터(SCR; Silicon Controlled Rectifier)구조에 기반 한 새로운 구조의 ESD(Electro-Static Discharge) 보호 소자를 제안하였다. 홀딩전압은 애노드단을 감싸고 있는 n-well에 p+ 캐소드를 확장시키고, 캐소드단을 n-well로 추가함으로써 홀딩전압을 증가시킬 수 있다. 제안된 소자는 높은 홀딩전압 특성으로 높은 래치업 면역성을 갖는다. 본 연구에서 제안된 소자의 전기적 특성, 온도특성, ESD 감내특성을 확인하기 위하여 TCAD 시뮬레이션 툴을 이용하여 시뮬레이션을 수행하였다. 시뮬레이션 결과 제안된 소자는 10.5V의 트리거 전압과 3.6V의 홀딩전압을 갖는다. 그리고 추가적인 n-well과 확장된 p+의 사이즈 변화로 4V이상의 홀딩전압을 갖는 것을 확인하였다.

Keywords

References

  1. Wang AZH. On-chip ESD protection for integrated circuit. An IC design perspective. 2nd ed. Kluwer Academic Publisher, 2002
  2. O.Semenov, H. Sarbishaei, M. Sachdev, ESD Protection Device and Circuit Design for Advanced CMOS Technologies, Netherlands, Springer, 2008
  3. V. Vashchenko, A. Concannon, M. ter Beek, P. Hopper, High holding voltage cascoded LVTSCR structures for 5.5-V tolerant ESD protection clamps, IEEE Trans. on Devices. and Materials Reliability, vol. 4, pp273-280, 2004 https://doi.org/10.1109/TDMR.2004.826584
  4. C. Russ, M. P. J. Mergens, J. Armer, P. Jozwiak, G.Kolluri, L. Avery, and K. Vergaegem, GGSCR: GGNMOS triggered silicon controlled rectifiers for ESD protection in deep submicron CMOS processes, in Proc. EOS/ESD Symp.,, pp.22-31, 2001
  5. J. Salcedo and J. J. Liou, A novel dual-polarity device with symmetrical/asymmetrical S-type I-V characteristics for ESD protection design, IEEE Electron Device Lett., vol.27, pp. 65-67, 2006 https://doi.org/10.1109/LED.2005.861601
  6. A Chatterjee and T. Polgreen, A low-voltage triggering SCR for on-chip ESD protection at output and input pads, IEEE Electron Device Lett., vol.12, pp.21-22, 1991 https://doi.org/10.1109/55.75685
  7. M.-D. Ker, H.-H. Chang, and C.-Y. Wu, A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS ICs, IEEE J, Solid-State Circuits, vol. 32, pp. 38-51, 1997 https://doi.org/10.1109/4.553176
  8. M.- D. Ker, and K.- C. Hsu, SCR devices with double-triggered technique for on-chip ESD protection in sub-quarter-micron silicided CMOS processes, IEEE Trans. Device Mater. Rel., vol. 3, pp. 58-68, 2003 https://doi.org/10.1109/TDMR.2003.815192
  9. J. A. Salcedo, J. J. Liou, and J. C. Bernier, Novel and robust silicon controlled rectifier(SCR) based devices fo on-chip ESD protection, IEEE Electron device Lett., vol. 25, pp. 658-660, 2004 https://doi.org/10.1109/LED.2004.834736
  10. S.-L. Jang, L.-S. Lin, S.-H. Li, Temperature-dependant dynamic triggering charactersitics of SCR-type ESD protection circuit Solid-State Electronics, 45, pp. 2005-2009, 2001 https://doi.org/10.1016/S0038-1101(01)00243-X