• Proceedings of the Korean Society of Tribologists and Lubrication Engineers Conference
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• 2003.11a
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• pp.329-334
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• 2003

Design of pre-compression region(trapping region) of the valve plate is an important element to minimize the pressure fluctuation in a cylinder and in discharge process, and pump noise. In this study, we tried to prove what the characteristics of the oil hydraulic pump would be according to the angle of the trapping region. Three kinds of asymmetrical valve plates were used. As a result, we found that by designing the trapping region, the slope of the pressure rise in the cylinder port from low-pressure suction region to high-pressure discharge region is relaxed and the pressure fluctuation width and the discharge pressure pulsation are reduced. Therefore, because the pump gets smooth pressure fluctuation and low fluid Impact, the pump noise is reduce.

• Proceedings of the KSME Conference
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• 2003.04a
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• pp.2071-2075
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• 2003

Pressure variation is one of the major sources on noise emission in the oil hydraulic piston pumps. Therefore, it is necessary to clarify about pressure variation characteristics of the oil hydraulic piston pumps to reduce noise. Pressure variations in a cylinder at trapping region were measured during pump working period with discharge pressures, rotational speeds. The effect of pre-compression of the discharge port with three types valve plates also investigated. It was found that the pressure variation characteristics of oil hydraulic piston pumps deeply related with pre-compression design of the discharge port. Also, it was found that the pressure overshoot at trapping region can reduce by use of pre-compression at the end of the discharge port in valve plate

• Journal of the Chungcheong Mathematical Society
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• v.33 no.1
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• pp.157-163
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• 2020

Conley introduced attracting sets and repelling sets for a flow on a topological space and showed that if f is a flow on a compact metric space, then 𝓡(f) = ⋂{A_U ∪ A*_U |U is a trapping region for f}. In this paper we introduce chain recurrent set, trapping region, attracting set and repelling set for a flow f on a TVS-cone metric space and prove that if f is a flow on a compact TVS-cone metric space, then 𝓡(f) = ⋂{A_U ∪ A*_U |U is a trapping region for f}.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.1
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• pp.54-60
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• 1994

In this paper, we present the analytical models for the change of the lateral electric field distribution and the velocity saturation region length with the electron trapping of stressed SC-PMOSFET in the saturation region. To derive the hot-electron-induced lateral electric field of stressed SC-PMOSFET. Ko's pseudo two dimensional box model in the saturation region which illustrates the analysis of the velocity saturation region is modified under the condition of electron trapping in the oxide near the drain region. From the results, we have the following lateral electric field in the y-direction, that is, E(y) ES1satT.cosh(y/l) qNS1tT.sinh(y/l)/lCox. It is shown that the trapped electrons influence the field in the drain region. decreasing the lateral electric field. Calculated velocity saturaion length increases with the trapped electrons. increasing the drain current of stressed SCPMOSFET. This results well explain the HEIP phenomenon of PMOSFET's.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.12
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• pp.77-87
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• 1993

PMOSFETs were studied on the effect of Hot-Carrier induced drain leakage current (Gate-Induced-Drain-Leakage). The result turned out that change in Vgl(drain voltage where 1pA/$\mu$m of drain leadage current flows) was largest in the Channel-Hot-Hole(CHH) injection condition and next was in dynamic stress and was smallest in electron trapping (Igmax) condition under various stress conditions. It was analyzed that if electron trapping occurrs in the overlap region of gate and drain(G/D), it reduces GIDL current due to increment of flat-band voltage(Vfb) and if CHH is injected, interface states(Nit) were generated and it increases GIDL current due to band-to-defect-tunneling(BTDT). Especially, under dynamic stress it was confirmed that increase in GIDL current will be high when electron injection was small and CHH injection was large. Therefore as applying to real circuit, low drain voltage GIDL(BTDT) was enhaced as large as CHH Region under various operating voltage, and it will affect the reliablity of the circuit.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.35 no.2
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• pp.131-134
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• 2011

We propose a spheroid chip that uses removable cell trapping barriers and that is capable of forming and extracting multicellular spheroids. By using a conventional well plate and flask, it is difficult to form small-sized spheroids, which resemble avascular 3D cell-cell interaction. It was difficult to extract spheroids using conventional microchips and fixed cell trapping barriers. The proposed chip, however, facilitates both formation and extraction of spheroids by using removable cell trapping barriers formed by membrane deflection. The cell trapping barriers, formed at the membrane pressure of 50 kPa, hold the cells in the trapping region at a cell inlet pressure of 145.155 Pa. After incubation for 24 h, the trapped cells form uniform spheroids. We successfully extract the spheroids at a cell inlet pressure of 5 kPa after removing the membrane pressure. The extracted spheroids have a diameter of $197.2{\pm}11.7Bm$ with a viability of $80.3{\pm}7.7%$. Using the proposed chip, uniform spheroids can be formed and these spheroids can be safely extracted for carrying out the post-processing of spheroids.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.163-163
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• 2015

The effect of nematic liquid crystal(5CB-4-Cyano-4'-pentylbiphenyl) on the amorphous indium gallium zinc oxide thin film transistors(a-IGZO TFTs) was investigated. Through dropping the 5CB on the a-IGZO TFT's channel layer which is deposited by RF-magnetron sputtering, properties of a-IGZO TFTs was dramatically improved. When drain bias was induced, 5CB molecules were oriented by Freedericksz transition generating positive charges to one side of dipoles. From increment of the capacitance by orientation of liquid crystals, the drain current was increased, and we analyzed these phenomena mathematically by using MOSFET model. Transfer characteristic showed improvement such as decreasing of subthreshold slope(SS) value 0.4 to 0.2 and 0.45 to 0.25 at linear region and saturation region, respectively. Furthermore, in positive bias system(PBS), prevention effect for electron trapping by 5CB liquid crystal dipoles was observed, which showing decrease of threshold voltage shift [(${\delta}V$]_TH) when induced +20V for 1~1000sec at the gate electrode.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.11a
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• pp.13-16
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• 1998

An anomalous current characteristics which show the superposition of a low current level and high current level at the subthreshold region when SONOSFETs are in memory states were investigated. We have assumed this phenomena were resulted from the effect of parasitic transistors by LOCOS isolation and were modeled to a parallel equivalent circuit of one memory transistor and two parasitic transistors. Theoretical curves are well fitted in measured log I$_{D}$-V$_{G}$ curves independent of channel width of memory devices. The difference between low current level and high current level is apparently decreased with decrease of channel width of devices because parasitic devices dominantly contribute to the current conduction with decrease of channel width of memory devices. As a result, we concluded that the LOCOS isolation has to selectively adopt in the design of process for charge-trap type NVSM.VSM.

• Journal of the Semiconductor & Display Technology
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• v.16 no.1
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• pp.65-69
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• 2017

This paper presents a Technology-CAD (TCAD) simulation of the characteristics of crystalline Si pillar array solar cells. The junction depth and the surface concentration of the solar cells were optimized to obtain the targeted sheet resistance of the emitter region. The diffusion model was determined by calibrating the emitter doping profile of the microscale silicon pillars. The dimension parameters determining the pillar shape, such as width, height, and spacing were varied within a simulation window from ${\sim}2{\mu}m$ to $5{\mu}m$. The simulation showed that increasing pillar width (or diameter) and spacing resulted in the decrease of current density due to surface area loss, light trapping loss, and high reflectance. Although increasing pillar height might improve the chances of light trapping, the recombination loss due to the increase in the carrier's transfer length canceled out the positive effect to the photo-generation component of the current. The silicon pillars were experimentally formed by photoresist patterning and electroless etching. The laboratory results of a fabricated Si pillar solar cell showed the efficiency and the fill factor to be close to the simulation results.

• Journal of Information Display
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• v.6 no.4
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• pp.6-10
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• 2005

The dependence of hysteresis characteristics in low temperature poly-Si (LTPS) thin film transistors (TFTs) on the gate-source voltage (Vgs) or the drain-source voltage (Vds) bias is investigated and discussed. The hysteresis levels in both p-type and n-type LTPS TFTs are independent of Vds bias but increase as the sweep range of Vgs increases. It has been found that the hysteresis in both p-type and n-type LTPS TFTs originated from charge trapping and de-trapping in the channel region rather than at the source/drain edges.