• Title/Summary/Keyword: Transmission Gate

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SOI CMOS Miniaturized Tunable Bandpass Filter with Two Transmission zeros for High Power Application (고 출력 응용을 위한 2개의 전송영점을 가지는 최소화된 SOI CMOS 가변 대역 통과 여파기)

  • Im, Dokyung;Im, Donggu
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.1
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    • pp.174-179
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    • 2013
  • This paper presents a capacitor loaded tunable bandpass chip filter using multiple split ring resonators (MSRRs) with two transmission zeros. To obtain high selectivity and minimize the chip size, asymmetric feed lines are adopted to make a pair of transmission zeros located on each side of passband. Compared with conventional filters using cross-coupling or source-load coupling techniques, the proposed filter uses only two resonators to achieve high selectivity through a pair of transmission zeros. In order to optimize selectivity and sensitivity (insertion loss) of the filter, the effect of the position of asymmetric feed line on transmission zeros and insertion loss is analyzed. The SOI-CMOS switched capacitor composed of metal-insulator-metal (MIM) capacitor and stacked-FETs is loaded at outer rings of MSRRs to tune passband frequency and handle high power signal up to +30 dBm. By turning on or off the gate of the transistors, the passband frequency can be shifted from 4GH to 5GHz. The proposed on-chip filter is implemented in 0.18-${\mu}m$ SOI CMOS technology that makes it possible to integrate high-Q passive devices and stacked-FETs. The designed filter shows miniaturized size of only $4mm{\times}2mm$ (i.e., $0.177{\lambda}g{\times}0.088{\lambda}g$), where ${\lambda}g$ denotes the guided wave length of the $50{\Omega}$ microstrip line at center frequency. The measured insertion loss (S21)is about 5.1dB and 6.9dB at 5.4GHz and 4.5GHz, respectively. The designed filter shows out-of-band rejection greater than 20dB at 500MHz offset from center frequency.

High-performance 94 GHz Single Balanced Mixer Based On 70 nm MHEMT And DAML Technology (70 nm MHEMT와 DAML 기술을 이용한 우수한 성능의 94 GHz 단일 평형 혼합기)

  • Kim Sung-Chan;An Dan;Lim Byeong-Ok;Beak Tae-Jong;Shin Dong-Hoon;Rhee Jin-Koo
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.4 s.346
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    • pp.8-15
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    • 2006
  • In this paper, the 94 GHz, low conversion loss, and high isolation single balanced mixer is designed and fabricated using GaAs-based metamorphic high electron mobility transistors (MHEMTs) with 70 nm gate length and the hybrid ring coupler with the micromachined transmission lines, dielectric-supported air-gapped microstrip lines (DAMLs). The 70 nm MHEMT devices exhibit DC characteristics with a drain current density of 607 mA/mm an extrinsic transconductance of 1015 mS/mm. The current gain cutoff frequency ($f_T$) and maximum oscillation frequency ($f_{max}$) are 320 GHz and 430 GHz, respectively. The fabricated hybrid ring coupler shows wideband characteristics of the coupling loss of $3.57{\pm}0.22dB$ and the transmission loss of $3.80{\pm}0.08dB$ in the measured frequency range of 85 GHz to 105 GHz. This mixer shows that the conversion loss and isolation characteristics are $2.5dB{\sim}>2.8dB$ and under -30 dB, respectively, in the range of $93.65GHz{\sim}94.25GHz$. At the center frequency of 94 GHz, this mixer shows the minimum conversion loss of 2.5 dB at a LO power of 6 dBm To our knowledge, these results are the best performances demonstrated from 94 GHz single balanced mixer utilizing GaAs-based HEMTs in terms of conversion loss as well as isolation characteristics.

Improved Electrical Properties by In Situ Nitrogen Incorporation during Atomic Layer Deposition of HfO2 on Ge Substrate (Ge 기판 위에 HfO2 게이트 산화물의 원자층 증착 중 In Situ 질소 혼입에 의한 전기적 특성 변화)

  • Kim, Woo-Hee;Kim, Bum-Soo;Kim, Hyung-Jun
    • Journal of the Korean Vacuum Society
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    • v.19 no.1
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    • pp.14-21
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    • 2010
  • Ge is one of the attractive channel materials for the next generation high speed metal oxide semiconductor field effect transistors (MOSFETs) due to its higher carrier mobility than Si. But the absence of a chemically stable thermal oxide has been the main obstacle hindering the use of Ge channels in MOS devices. Especially, the fabrication of gate oxide on Ge with high quality interface is essential requirement. In this study, $HfO_xN_y$ thin films were prepared by plasma-enhanced atomic layer deposition on Ge substrate. The nitrogen was incorporated in situ during PE-ALD by using the mixture of nitrogen and oxygen plasma as a reactant. The effects of nitrogen to oxygen gas ratio were studied focusing on the improvements on the electrical and interface properties. When the nitrogen to oxygen gas flow ratio was 1, we obtained good quality with 10% EOT reduction. Additional analysis techniques including X-ray photoemission spectroscopy and high resolution transmission electron microscopy were used for chemical and microstructural analysis.

A DC Reference Fluctuation Reduction Circuit for High-Speed CMOS A/D Converter (고속 CMOS A/D 변환기를 위한 기준전압 흔들림 감쇄 회로)

  • Park Sang-Kyu;Hwang Sang-Hoon;Song Min-Kyu
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.6 s.348
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    • pp.53-61
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    • 2006
  • In high speed flash type or pipelining type A/D Converter, the faster sampling frequency is, the more the effect of DC reference fluctuation is increased by clock feed-through and kick-back. When we measure A/D Converter, further, external noise increases reference voltage fluctuation. Thus reference fluctuation reduction circuit must be needed in high speed A/D converter. Conventional circuit simply uses capacitor but layout area is large and it's not efficient. In this paper, a reference fluctuation reduction circuit using transmission gate is proposed. In order to verify the proposed technique, we designed and manufactured 6bit 2GSPS CMOS A/D converter. The A/D converter is based on 0.18um 1-poly 5-metal N-well CMOS technology, and it consumes 145mW at 1.8V power supply. It occupies chip area of $977um\times1040um$. Experimental result shows that SNDR is 36.25 dB and INL/DNL ${\pm}0.5LSB$ when sampling frequency is 2GHz.

Dynamic Bandwidth Allocation Algorithm with Two-Phase Cycle for Ethernet PON (EPON에서의 Two-Phase Cycle 동적 대역 할당 알고리즘)

  • Yoon, Won-Jin;Lee, Hye-Kyung;Chung, Min-Young;Lee, Tae-Jin;Choo, Hyun-Seung
    • The KIPS Transactions:PartC
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    • v.14C no.4
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    • pp.349-358
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    • 2007
  • Ethernet Passive Optical Network(EPON), which is one of PON technologies for realizing FTTx(Fiber-To-The-Curb/Home/Office), can cost-effectively construct optical access networks. In addition, EPON can provide high transmission rate up to 10Gbps and it is compatible with existing customer devices equipped with Ethernet card. To effectively control frame transmission from ONUs to OLT EPON can use Multi-Point Control Protocol(MPCP) with additional control functions in addition to Media Access Control(MAC) protocol function. For EPON, many researches on intra- and inter-ONU scheduling algorithms have been performed. Among the inter-ONU scheduling algorithms, IPS(Interleaved Polling with Stop) based on polling scheme is efficient because OLT assigns available time portion to each ONU given the request information from all ONUs. Since the IPS needs an idle time period on uplink between two consecutive frame transmission periods, it wastes time without frame transmissions. In this paper, we propose a dynamic bandwidth allocation algorithm to increase the channel utilization on uplink and evaluate its performance using simulations. The simulation results show that the proposed Two-phase Cycle Danamic Bandwidth Allocation(TCDBA) algorithm improves the throughput about 15%, compared with the IPS and Fast Gate Dynamic Bandwidth Allocation(FGDBA). Also, the average transmission time of the proposed algorithm is lower than those of other schemes.

The $ Si-SiO_2$ interface structure of a SIMOX SOI formed by 100keV $O^+$ ion beam (100 keV $O^+$ 이온 빔에 의한 SIMOX SOI의 $ Si-SiO_2$계면 구조)

  • 김영필;최시경;김현경;문대원
    • Journal of the Korean Vacuum Society
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    • v.7 no.1
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    • pp.35-42
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    • 1998
  • - The Si-$SiO_2$ interface of silicon on insulator (SOI) formed by 100 keV $O^+$ was ohserved using high resolution transmission electron microscopy (HRTEM), before and after annealing. The interface of as-implanted sample, ~$5\times 10^{17}\textrm{cm}^{-2}O^+$ implanted at $550^{\circ}C$ was very rough and it has many defectsoxide precipitate, stacking fault, coesite $SiO_2$ etc. However, the interface became flat by high temperature annealing at $1300^{\circ}C$ for 4 hour. It's roughness, observed by HRTEM, was comparable to the interface roughness of 3 keV $O_2^\;+$ ion beam oxide and -6 nm gate oxide formed by thermal oxidation.

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Application of Graphene in Photonic Integrated Circuits

  • Kim, Jin-Tae;Choe, Seong-Yul;Choe, Chun-Gi
    • Proceedings of the Korean Vacuum Society Conference
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    • 2012.02a
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    • pp.196-196
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    • 2012
  • Graphene, two-dimensional one-atom-thick planar sheet of carbon atoms densely packed in a honeycomb crystal lattice, has grabbled appreciable attention due to its extraordinary mechanical, thermal, electrical, and optical properties. Based on the graphene's high carrier mobility, high frequency graphene field effect transistors have been developed. Graphene is useful for photonic components as well as for the applications in electronic devices. Graphene's unique optical properties allowed us to develop ultra wide-bandwidth optical modulator, photo-detector, and broadband polarizer. Graphene can support SPP-like surface wave because it is considered as a two-dimensional metal-like systems. The SPPs are associated with the coupling between collective oscillation of free electrons in the metal and electromagnetic waves. The charged free carriers in the graphene contribute to support the surface waves at the graphene-dielectric interface by coupling to the electromagnetic wave. In addition, graphene can control the surface waves because its charge carrier density is tunable by means of a chemical doping method, varying the Fermi level by applying gate bias voltage, and/or applying magnetic field. As an extended application of graphene in photonics, we investigated the characteristics of the graphene-based plasmonic waveguide for optical signal transmission. The graphene strips embedded in a dielectric are served as a high-frequency optical signal guiding medium. The TM polarization wave is transmitted 6 mm-long graphene waveguide with the averaged extinction ratio of 19 dB at the telecom wavelength of $1.31{\mu}m$. 2.5 Gbps data transmission was successfully accomplished with the graphene waveguide. Based on these experimental results, we concluded that the graphene-based plasmonic waveguide can be exploited further for development of next-generation integrated photonic circuits on a chip.

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Eletrostatic Discharge Effects on AlGaN/GaN High Electron Mobility Transistor on Sapphire Substrate (사파이어 기판을 사용한 AlGaN/GaN 고 전자이동도 트랜지스터의 정전기 방전 효과)

  • Ha Min-Woo;Lee Seung-Chul;Han Min-Koo;Choi Young-Hwan
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.54 no.3
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    • pp.109-113
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    • 2005
  • It has been reported that the failure phenomenon and variation of electrical characteristic due to the effect of electrostatic discharge(ESD) in silicon devices. But we had fess reports about the phenomenon due to the ESD in the compound semiconductors. So there are a lot of difficulty to the phenomenon analysis and to select the protection method of main circuits or the devices. It has not been reported that the relation between the ESD stress and GaN devices, which is remarkable to apply the operation in high temperature and high voltage due to the superior material characteristic. We studied that the characteristic variation of the AlGaN/GaN HEMT current, the leakage current, the transconductance(gm) and the failure phenomenon of device due to the ESD stress. We have applied the ESD stress by transmission line pulse(TLP) method, which is widely used in ESD stress experiments, and observed the variation of the electrical characteristic before and after applying the ESD stress. The on-current trended to increase after applying the ESD stress. The leakage current and transconductance were changed slightly. The failure point of device was mainly located in middle and edge sides of the gate, was considered the increase of temperature due to a leakage current. The GaN devices have poor thermal characteristic due to usage of the sapphire substrate, so it have been shown to easily fail at low voltage compared to the conventional GaAs devices.

A study on the fiber orientation and mechanical characteristics of injection molded fiber-reinforced plastic for the rigidity improvement of automotive parts (자동차 부품의 강성 보강을 위한 섬유강화 플라스틱 사출성형품의 섬유 배향 및 기계적 특성에 관한 연구)

  • Eui-Chul Jeong;Yong-Dae Kim;Jeong-Won Lee;Seok-Kwan Hong;Sung-Hee Lee
    • Design & Manufacturing
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    • v.16 no.4
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    • pp.24-33
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    • 2022
  • Fiber-reinforced plastics(FRPs) have excellent specific stiffness and strength, so they are usually used as automotive parts that require high rigidity and lightweight instead of metal. However, it is difficult to predict the mechanical properties of injection molded parts due to the fiber orientation and breakage of FRPs. In this paper, the fiber orientation characteristics and mechanical properties of injection molded specimens were evaluated in order to fabricate automotive transmission side covers with FRPs and design a rib structure for improvement of their rigidity. The test molds were designed and manufactured to confirm the fiber orientation characteristics of each position of the injection molded standard plate-shaped specimens, and the tensile properties of the specimens were evaluated according to the injection molding conditions and directions of specimens. A gusset-rib structure was designed to improve the additional structural rigidity of the target products, and a proper rib structure was selected through the flexural tests of the rib-structured specimens. Based on the evaluation of fiber orientation and mechanical characteristics, the optimization analyses of gate location were performed to minimize the warpage of target products. Also, the deformation analyses against the internal pressure of target product were performed to confirm the rigidity improvement by gusset-rib structure. As a result, it could be confirmed that the deformation was reduced by 27~37% compared to the previous model, when the gusset-rib structure was applied to the joining part of the target products.

Modeling and Analysis of the KEPCO UPFC System by EMTDC/PSCAD

  • Yoon, Jong-Su;Kim, Soo-Yeol;Chang, Byung-Hoon;Lim, Seong-Joo;Choo, Jin-Boo
    • KIEE International Transactions on Power Engineering
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    • v.3A no.3
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    • pp.148-154
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    • 2003
  • This paper describes the development of KEPCO's 80MVA UPFC electromagnetic transient model and the analysis of its performance in the actual Korean power system. KEPCO's 80MVA UPFC is currently undergoing installation and will be ready for commercial operation from the year 2003. In order to apply a new FACTS device such as the UPFC to the actual power system, the utility needs, in advance, both load flow stability studies and transient studies. Therefore, KEPRI, the research institute of KEPCO, developed a detailed transient analysis model that is based on the actual UPFC S/W algorithm and H/W specifications. This simulation model is implemented by an EMTDC/PSCAD package. The results of the simulation show the effectiveness of UPFC operation in the KEPCO power system.