• Title/Summary/Keyword: Transister

Search Result 18, Processing Time 0.023 seconds

A Study on Design of High Speed-Low Voltage LVDS Driver Circuit Using BiCMOS Technology (고속 저 전압 BiCMOS LVDS 회로 설계에 관한 연구)

  • Lee, Jae-Hyun;Yuk, Seung-Bum;Koo, Yong-Seo;Kim, Kui-Dong;Kwon, Jong-Ki
    • Proceedings of the IEEK Conference
    • /
    • 2006.06a
    • /
    • pp.621-622
    • /
    • 2006
  • This paper presents the design of LVDS(Low-Voltage-Differential-Signaling) driver circuit for Gb/s-per-pin operation using BiCMOS process technology. To reduce chip area, LVDS driver's switching devices were replaced with lateral bipolar devices. The designed lateral bipolar transister's common emitter current gain($\beta$) is 20 and device's emitter size is 2*10um. Also the proposed LVDS driver is operated at 2.5V and the maximum data rate is 2.8Gb/s approximately.

  • PDF

A study on the Control of Characteristic in the Analog Active Element for System Stabilization (시스템 안정화를 위한 아날로그 능동 소자의 특성 제어에 관한 연구)

  • 이근호;방준호;김동용
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.25 no.6B
    • /
    • pp.1114-1119
    • /
    • 2000
  • In this paper, a current comparative frequency automatic tuning circuit for the CMOS bandpass filter are designed with the new architecture. And also, when the designed circuit is compared the typical tuning circuit, it has very simple architecture that is composed of the current comparator and charge pump and operated in 2V power supply. The proposed tuning circuit automatically compensate the difference between the operating current of the integrator and the reference current which is specified. Using CMOS 0.25um parameter, a CMOS bandpass active filter with center frequency(fo=100MHz) is designed, and according to the transister size the variation of the center frequency is simulated. As the HSPICE simulation results, the tuning operating of the proposed current comparative frequency automatic tuning circuit is verified.

  • PDF

Design and Implementation of High Sensitivity Single Power Factor Meter. (고감도 단상력률계의 설계 및 시작)

  • 박정후
    • Journal of the Korean Society of Fisheries and Ocean Technology
    • /
    • v.15 no.2
    • /
    • pp.55-60
    • /
    • 1979
  • The forming and design method of single power factor meter is suggested and the sensitive phase angle detect circuit of current and voltage of load was dealt with. In this paper, in order to control and detect of phase angle of the current and voltage, operational amplifier comparator circuit and R-C phase shift circuit was used, and to detect the controlled voltage wave form, the transister chopper pair circuit was used. The test result of this power factor meter was good and reliable at the full range of power factor.

  • PDF

Synthesis and property analysis of hydropolysilanes for amorphous and polycrystalline silicon (무정형 또는 다결정성 규소를 위한 하이드로폴리실란의 합성과 물성 분석)

  • Ahn, Sun-Ah;Lee, Sung-Hwan;Song, Young-Sang;Lee, Gyu-Hwan
    • Analytical Science and Technology
    • /
    • v.24 no.2
    • /
    • pp.105-112
    • /
    • 2011
  • Syntheses and property analysis of hydropolysilanes were studied. Those hydropolysilanes can be utilized as precursors for amorphous silicon and polycrystallline silicon for the purpose of the solar cell and the thin film transister for the next generation's semiconductors. Most important characteristics of this study are to find optimized conditions for the synthesis and property analysis of soluble hydropolysilanes. Also the possibility of pyrolytic conversion to amorphous and polycrystalline silicon was investigated.

Influence of Perfluorinated Polymer Passivation on AlGaN/GaN High-electron-mobility Transistors (질화갈륨계 고전자이동도 트랜지스터에 대한 불소계 고분자 보호막의 영향)

  • Jang, Soohwan
    • Korean Chemical Engineering Research
    • /
    • v.48 no.4
    • /
    • pp.511-514
    • /
    • 2010
  • Perfluorinated polymer($Cytop^{TM}$) was deposited on selective area of AlGaN/GaN HEMT structure using low cost and simple spin-coating method, and the electrical characteristics of the device was analyzed for application of passivation layer on semiconductors. Gate lag measurement results of $Cytop^{TM}$ passivated and unpassivated HEMT were compared. Passivated device shows improved 65 % pulsed drain current of dc mode value. Rf measurements were also performed. $Cytop^{TM}$ passivated HEMT have similar rf performance to PECVD grown $Si_3N_4$ passivated device. $Cytop^{TM}$ passivation layer may play an important role in mitigating surface state trapping in the region between gate and drain.

Threshold Voltage Control of Pentacene Thin-Film Transistor with Dual-Gate Structure

  • Koo, Jae-Bon;Ku, Chan-Hoe;Lim, Sang-Chul;Lee, Jung-Hun;Kim, Seong-Hyun;Lim, Jung-Wook;Yun, Sun-Jin;Yang, Yong-Suk;Suh, Kyung-Soo
    • Journal of Information Display
    • /
    • v.7 no.3
    • /
    • pp.27-30
    • /
    • 2006
  • This paper presents a comprehensive study on threshold voltage $(V_{th})$ control of organic thin-film transistors (OTFTs) with dual-gate structure. The fabrication of dual-gate pentacene OTFTs using plasma-enhanced atomic layer deposited (PEALD) 150 nm thick $Al_{2}O_{3}$ as a bottom gate dielectric and 300 nm thick parylene or PEALD 200 nm thick $Al_{2}O_{3}$ as both a top gate dielectric and a passivation layer was investigated. The $V_{th}$ of OTFT with 300 nm thick parylene as a top gate dielectric was changed from 4.7 V to 1.3 V and that with PEALD 200 nm thick $Al_{2}O_{3}$ as a top gate dielectric was changed from 1.95 V to -9.8 V when the voltage bias of top gate electrode was changed from -10 V to 10 V. The change of $V_{th}$ of OTFT with dual-gate structure was successfully investigated by an analysis of electrostatic potential.

A SIMULINK Modeling for a Fractional-N Frequency Synthesizer (SIMULINK를 이용한 Fractional-N 주파수합성기의 모델링 기법)

  • Kim, In-Jeong;Seo, Woo-Hyong;Ahn, Jin-Oh;Kim, Dae-Jeong
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.44 no.4
    • /
    • pp.103-109
    • /
    • 2007
  • This paper presents behavioral models using SIMULINK and Verilog-a for a PLL based fractional-N frequency synthesizer. By adopting a top-down approach along with the traditional bottom-up transistor level design in parallel, the design time is greatly shortened, and a co-verification method for both the digital and the analog part is considered. Under this consideration, the SIMULINK modeling reduces simulation time and easily estimates the PLL's performance on the top level. Verilog-a is able to verify the feasibility of each blocks at first hand because it is compatible with transister level circuits. Then, an efficient way of the design is presented by comparing the results of both models.

A Study on the Reversible SCR Servo Amplifier (정역전이 가능한 SCR 서보증폭기에 관한 연구)

  • Ahn, B. W.;Park, S. K.
    • Journal of the Korean Society of Fisheries and Ocean Technology
    • /
    • v.31 no.2
    • /
    • pp.190-198
    • /
    • 1995
  • Many industrial servo amplifiers employ power transister as output device. Thyristor converters are not adopted to drive servo motor, although thyristor is superior to power TR in power rating, noise immunity, price, and size. The reason is, thyristor has no ability of self turn - off. Here in this paper line commutation, in which thyristor is turned off naturally since cathode voltage is higher than anode as time goes by, is employed to turn on thyristor with a delicate sequence. We developed thyristor servo amplifier which does not cause any damage on thyristor because it is designed to prevent triggering the two SCRs in the same arm simultaneously. And it was made clearly how to trigger SCR without any power line shorting and also harmonic analysis is carried out with the aid of FFT analyzer and proved that it can be used even severe reactive load. The designed circuit operated as a good DC amplifier in conventinal servomotor and the results can be use as a position control system application.

  • PDF