• 전자공학회논문지 IE
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• v.49 no.1
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• pp.1-6
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• 2012

For the performance improvement of a time-to-digital converter(TDC), a 2-stage high resolution TDC has been designed by using a 2-stage vernier time amplifier(2-S VTA). The two stage vernier time amplifier which has a gain over 64 of the resolution can enhance the resolution of the whole two stage TDC. Because of using a vernier TDC, the structure is not limited to advanced processes for achieving high resolution. The proposed TDC has been designed in a $0.18{\mu}m$ CMOS process and simulated with a 1.8V supply voltage. The entire input range is 512ps, and the full resolution 0.125ps.

• ETRI Journal
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• v.33 no.3
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• pp.366-373
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• 2011

In this paper, we propose a low-power all-digital phase-locked loop (ADPLL) with a wide input range and a high resolution time-to-digital converter (TDC). The resolution of the proposed TDC is improved by using a phase-interpolator and the time amplifier. The phase noise of the proposed ADPLL is improved by using a fine resolution digitally controlled oscillator (DCO) with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. The die area of the ADPLL is 0.8 $mm^2$ using 0.13 ${\mu}m$ CMOS technology. The frequency resolution of the TDC is 1 ps. The DCO tuning range is 58% at 2.4 GHz and the effective DCO frequency resolution is 0.14 kHz. The phase noise of the ADPLL output at 2.4 GHz is -120.5 dBc/Hz with a 1 MHz offset. The total power consumption of the ADPLL is 12 mW from a 1.2 V supply voltage.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.9
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• pp.54-61
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• 2016

A 6-Gbps single-ended receiver with a linear equalizer and a self-reference generator is proposed for a high-speed interface with the double data rate. The proposed single-ended receiver uses a common gate amplifier to increase a voltage gain for an input signal with low voltage level. The continuous-time linear equalizer which reduces gain to the low frequencies and achieves high-frequency peaking gain is implemented in the common gate amplifier. Furthermore, a self-reference generator, which is controlled with the resolution 2.1 mV using digital averaging method, is implemented to maximize the voltage margin by removing the offset noise of the common gate amplifier. The proposed single-ended receiver is designed using a 65-nm CMOS process with 1.2-V supply and consumes the power of 15 mW at the data rate of 6 Gbps. The peaking gain in the frequency of 3 GHz of the designed equalizer is more than 5 dB compared to that in the low frequency.

• Journal of IKEEE
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• v.22 no.2
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• pp.408-412
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• 2018

In this paper, a 26GHz variable gain amplifier fabricated using a 40nm CMOS process is studied. In the case of an automobile radar using 79 GHz, it is advantageous in designing and driving to drive down to a low frequency band or to use a low frequency band before up conversion rather than designing and matching the entire circuit to 79 GHz in terms of frequency characteristics. In the case of a Phased Array System that uses time delay through TTD (True Time Delay) in practice, down conversion to a lower frequency is advantageous in realizing a real time delay and reducing errors. For a VGA (Variable Gain Amplifier) operating in the 26GHz frequency band that is 1/3 of the frequency of 79GHz, VDD : 1V, Bias 0.95V, S11 is designed to be <-9.8dB (Mea. High gain mode) and S22 < (Mea. high gain mode), Gain: 2.69dB (Mea. high gain mode), and P1dB: -15 dBm (Mea. high gain mode). In low gain mode, S11 is <-3.3dB (Mea. Low gain mode), S22 <-8.6dB (Mea. low gain mode), Gain: 0dB (Mea. low gain mode), P1dB: -21dBm (Mea. Low gain mode).

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.834-837
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• 2005

In this paper, we describe the method of non-invasive blood pressure measurement using pulse wave transit time(PWTT). PWTT is a new parameter involved with a vascular that can indicate the change of BP. PWTT is measured by continuous monitoring of ECG and pulse wave. No additional sensors or modules are required. In many cases, the change of PWTT correlates with the change of BP. We measure pulse wave using the photo plethysmograph(PPG) sensor in an earlobe and we measure ECG using the ECG monitoring device our made in the chest. The measurement device for detecting pulse wave consists of infrared LED for transmitted light illumination, pin photodiode as light detector, amplifier and filter. We composed 0.5Hz high pass, 60Hz notch and 10Hz low pass filter. ECG measurement device consists of multiplexer, amplifier, filter, micro-controller and RF module. After amplification and filtering, ECG signal and pulse wave is fed through micro-controller. We performed the initial work towards the development of ambulatory BP monitoring system using PWTT. An earlobe is suitable place to measure PPG signal without the restraint in daily work. From the results, we can know that the dependence of PWTT on BP is almost linear and it is possible to monitoring an individual BP continuously after the individual calibration.

• Journal of the Korean Chemical Society
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• v.35 no.6
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• pp.713-719
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• 1991

Electrochemical impedance measurement system using Fourier transform was constructed in the range of the frequencies up to 100 kHz. This system consists of pseudo-random noise generator, specially designed potentiostat, fast data acquisition system, system controller, and computer interface. The performance of the constructed system was found to be almost same as the commercially available system using lock-in amplifier. Measuring time was significantly reduced because the minimum time for the measurement depended on one cycle of the lowest frequency used. It would be possible to study time-varying electrochemical impedance systems such as the initial stages of corrosion processes using this system.

• Journal of Electrical Engineering and Technology
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• v.1 no.4
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• pp.409-413
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• 2006

This paper deals with the design and testing of a simulator system for microgrids with distributed generations. This system is composed of a Real Time Digital Simulator (RTDS) and a power amplifier. The RTDS parts are operated for real time simulation for the microgrid model and the distributed generation source model. The power amplifiers are operated fur amplification of the RTDS's simulated output signal, which is a node voltage of the microgrid and distributed generation source. In this paper, we represent an RTDS system design, specification and test results of a power amplifier and simulation results of a PV (Photovoltaic) system and wind turbine system. The proposed system is applicable for development and performance testing of a PCS (Power Conversion System) for renewable energy sources.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.2
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• pp.299-308
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• 2008

This paper proposes a new design specification-based band fault modelling technique that can test design specification in a time domain. The band fault model is defined and the conditions of band fault model are gained as normal operation regions are defined. And the conditions of band fault model are used in a 5.25GHz low noise amplifier, then 9 band fault models that can detect hard and parametric faults of active and passive devices are obtained.

• Journal of IKEEE
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• v.25 no.2
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• pp.234-242
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• 2021

In case implementation of microwave photonic (MWP) systems for phased array radars (PARs), noise and time delay error should be minimized to obtain accurate beam direction. Time delay error in MWP systems is generated from signal noise and timing jitter. In this paper, noise and timing jitter in MWP systems for PAR is researched, also according to the amplification of an erbium-doped fiber amplifier, noise and timing jitter variation is verified by an experiment. Timing jitter is decreased and SNR is increased if we amplify the signal by using an erbium-doped fiber amplifier, up to the amplification rate of signal and noise is similar.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.87-93
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• 2010

This paper presents a high resolution, wide input range 2-step time-to-digital converter used in digital PLL. TDC is used to compare the DPLL output frequency with reference frequency and should be implemented with high resolution to improve the phase noise of DPLL. The conventional TDC consists of delay line realized inverters, whose resolution is determined by delay time of inverter and transistor size, resulting in limited resolution. In this paper, 2-step TDC with phase-interpolation and Time Amplifier is proposed to meet the high resolution and wide input range by implement the delay time less than an inverter delay. The gain of Time Amplifier is improved by using the delay time difference between two inverters. It is implemented in $0.13{\mu}m$ CMOS process and the die area is $800{\mu}m{\times}850{\mu}m$ Current consumption is 12 mA at the supply voltage of 1.2 V. The resolution and input range of the proposed TDC are 0.357 ps and 200 ps, respectively.