Browse > Article

A Design of 0.357 ps Resolution and 200 ps Input Range 2-step Time-to-Digital Converter  

Park, An-Soo (Department of Electronic Engineering, Konkuk University)
Park, Joon-Sung (Department of Electronic Engineering, Konkuk University)
Pu, Young-Gun (Department of Electronic Engineering, Konkuk University)
Hur, Jeong (Department of Electronic Engineering, Konkuk University)
Lee, Kang-Yoon (Department of Electronic Engineering, Konkuk University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.47, no.5, 2010 , pp. 87-93 More about this Journal
Abstract
This paper presents a high resolution, wide input range 2-step time-to-digital converter used in digital PLL. TDC is used to compare the DPLL output frequency with reference frequency and should be implemented with high resolution to improve the phase noise of DPLL. The conventional TDC consists of delay line realized inverters, whose resolution is determined by delay time of inverter and transistor size, resulting in limited resolution. In this paper, 2-step TDC with phase-interpolation and Time Amplifier is proposed to meet the high resolution and wide input range by implement the delay time less than an inverter delay. The gain of Time Amplifier is improved by using the delay time difference between two inverters. It is implemented in $0.13{\mu}m$ CMOS process and the die area is $800{\mu}m{\times}850{\mu}m$ Current consumption is 12 mA at the supply voltage of 1.2 V. The resolution and input range of the proposed TDC are 0.357 ps and 200 ps, respectively.
Keywords
Time-to-Digital Converter; Phase-Interpolation; Time-Amplifier; 2-step TDC; ADPLL;
Citations & Related Records
연도 인용수 순위
  • Reference
1 Dudek. P., Szczepanski, S., Hatfield. J.V., "A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line", IEEE J.Solid-State Circuits, Vol. 35, Issue 2, pp. 240-247, February. 2000.   DOI   ScienceOn
2 Henzler. S., Koeppe. S., Lorenz. D., Kamp. W., Kuenemund. R., Schmitt-Landsiedel. D., "A Local Passive Time Interpolation Concept for Variation-Tolerant High-Resolution Time-to- Digital Conversion", IEEE J. Solid-State Circuits, Vol. 43, Issue 7, pp. 1666-1676, July 2008   DOI
3 Minjae Lee, Abidi. A.A., "A 9 b, 1.25 ps Resolution Coarse-Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue", IEEE J. Solid-State Circuits, Vol. 43, Issue 4, pp. 769-777, April 2008.   DOI
4 Tonietto, R., Zuffetti, E., Castello, R., Bietti, I., "A 3MHz Bandwidth Low Noise RF All Digital PLL with 12ps Resolution Time to Digital Converter", Solid-State Circuits Conference, 2006. ESSCIRC 2006. Proceedings of the 32nd European, pp. 150-153, September, 2006.
5 Minjae Lee, Heidari. M. E., Abidi. A. A., "A Low-Noise Wideband Digital Phase-Locked Loop Based on a Coarse-Fine Time-to-Digital Converter With Subpicosecond Resolution", IEEEJ.Solid-State Circuits, Vol. 44, Issue 10, pp. 2808-2816, October. 2009.   DOI
6 Staszewski. R.B., Balsara. P.T., "Phase-domain all-digital phase-locked loop", IEEE Trans. on Circuits and Systems II Express Briefs, Vol. 52, Issue 3, pp. 159-163, March 2005.   DOI