• Title/Summary/Keyword: Time Synchronous

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IoT Security Channel Design Using a Chaotic System Synchronized by Key Value (키값 동기된 혼돈계를 이용한 IoT의 보안채널 설계)

  • Yim, Geo-Su
    • The Journal of the Korea institute of electronic communication sciences
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    • v.15 no.5
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    • pp.981-986
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    • 2020
  • The Internet of Things refers to a space-of-things connection network configured to allow things with built-in sensors and communication functions to interact with people and other things, regardless of the restriction of place or time.IoT is a network developed for the purpose of services for human convenience, but the scope of its use is expanding across industries such as power transmission, energy management, and factory automation. However, the communication protocol of IoT, MQTT, is a lightweight message transmission protocol based on the push technology and has a security vulnerability, and this suggests that there are risks such as personal information infringement or industrial information leakage. To solve this problem, we designed a synchronous MQTT security channel that creates a secure channel by using the characteristic that different chaotic dynamical systems are synchronized with arbitrary values in the lightweight message transmission MQTT protocol. The communication channel we designed is a method of transmitting information to the noise channel by using characteristics such as random number similarity of chaotic signals, sensitivity to initial value, and reproducibility of signals. The encryption method synchronized with the proposed key value is a method optimized for the lightweight message transmission protocol, and if applied to the MQTT of IoT, it is believed to be effective in creating a secure channel.

Identification of Motor Parameters and Improvement of Voltage Error for Improvement of Back-emf Estimation in Sensorless Control of Low Speed Operation (저속 센서리스 제어의 역기전력 추정 성능 향상을 위한 모터 파라미터 추정과 전압 오차의 개선)

  • Kim, Kyung-Hoon;Yun, Chul;Cho, Nae-Soo;Jang, Min-Ho;Kwon, Woo-Hyen
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.67 no.5
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    • pp.635-643
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    • 2018
  • This paper propose a method to identify the motor parameters and improve input voltage error which affect the low speed position error of the back-emf(back electromotive force) based sensorless algorithm and to secure the operation reliability and stability even in the case where the load fluctuation is severe and the start and low speed operation frequently occurs. In the model-based observer used in this paper, stator resistance, inductance, and input voltage are particularly influential factors on low speed performance. Stator resistance can cause resistance value fluctuation which may occur in mass production process, and fluctuation of resistance value due to heat generated during operation. The inductance is influenced by the fluctuation due to the manufacturing dispersion and at a low speed where the change of the current is severe. In order to find stator resistance and inductance which have different initial values and fluctuate during operation and have a large influence on sensorless performance at low speed, they are commonly measured through 2-point calculation method by 2-step align current injection. The effect of voltage error is minimized by offsetting the voltage error. In addition, when the command voltage is used, it is difficult to estimate the back-emf due to the relatively large distortion voltage due to the dead time and the voltage drop of the power device. In this paper, we propose a simple circuit and method to detect the voltage by measuring the PWM(Pulse Width Modulation) pulse width and compensate the voltage drop of the power device with the table, thereby minimizing the position error due to the exact estimation of the back-emf at low speed. The suitability of the proposed algorithm is verified through experiment.

An Innovative Solution for the Power Quality Problems in Induction Motor by Using Silica and Alumina Nano Fillers Mixed Enamel for the Coatings of the Windings

  • Mohanadasse, K.;Sharmeela, C.;Selvaraj, D. Edison
    • Journal of Electrical Engineering and Technology
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    • v.10 no.4
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    • pp.1621-1625
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    • 2015
  • Power quality has always been a concern of power engineers. Certainly an argument can be successfully made that most parts of power engineering have the ultimate objective to improve power quality. AC motors were widely used in industrial and domestic applications. Generally, AC motors were of two types: Induction and Synchronous motors. In motor many parameters like different load cycling, switching, working in hot weather and unbalances creates harmonics which creates major reasons for temperature rise of the motors. Due to high peak value of voltage, harmonics can weaken insulation in cables, windings and capacitors and different electronic components. Higher value of harmonics increase the motor current and decrease the power factor which will reduce the life time of the motor and increase the overall rating of all electrical equipments. Harmonics reduction of all the motors in India will save more power. Coating of windings of the motor with nano fillers will reduce the amount of harmonics in the motor. Based on the previous project works, actions were taken to use the enamel filled with various nano fillers for the coating of the windings of the different AC motors. Ball mill method was used to convert the micro particles of Al2O3, SiO2, TiO2, ZrO2 and ZnO into nano particles. SEM, TEM and XRD were used to augment the particle size of the powder. The synthesized nano powders were mixed with the enamel by using ultrasonic vibrator. Then the enamel mixed with the nano fillers was coated to the windings of the several AC motors. Harmonics were measured in terms of various indices like THD, VHD, CHD and DIN by using Harmonic analyzer. There are many other measures and indices to describe power quality, but none is applicable in all cases and in many instances, these indices may hide more than they show. Sometimes power quality indices were used as a basis of comparison and standardization. The efficiency of the motors was increased by 5 – 10 %. The thermal withstanding capacity of the motor was increased by 5º to 15º C. The harmonics of the motors were reduced by 10 – 50%.

LONGITUDINAL AND SEASONAL VARIATIONS OF THE ELECTRON TEMPERATURE AND DENSITY IN THE LOW_LATITUDE TOPSIDE IONOSPHERE OBSERVED BY KOMPSAT-1 (다목적 실용위성 1호로 측정한 저위도 상부 이온층의 전자 온도와 전자 밀도의 경도 및 계절별 변화)

  • Kim, Hee-jun;Park, Sun-Mie;Lee, Jae-Jin;Lee, En-sang;Min, Kyoung-Wook;Han, Won-yong;Nam, Uk-Won;Jin, Ho
    • Journal of Astronomy and Space Sciences
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    • v.19 no.2
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    • pp.123-132
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    • 2002
  • The electron density and temperature in the topside ionosphere are observed by the ionosphere Measurement Sensor (IMS) onboard the KOMPSAT-1, which has the sun-synchronous orbit of the altitude of 685 km and the orbital inclination of $98^{\circ}$ with a descending node at 22:50LT. Observations have been analyzed to determine the seasonal variations of the electron density and temperature in the low-latitude region. Only the night-time (22:50LT) behavior on magnetically quiet days (Kp < 4) has been examined. Observations show a strong longitudinal and seasonal variation. Generally, in the dip equator the density increases and the temperature decreases. In equinox the latitudinal distributions of the electron density and temperature are quite symmetric about the dip equator. However, the local maximum of the density and the local minimum of the temperature shift toward the Northern hemisphere in summer solstice but the Southern hemisphere in winter solstice. Such variations are due to the influences of field-aligned plasma transport induced by F region neutral wind. Compared with the IRI95 model, the observed electron density and temperature show significant differences from those predicted by the IRI95 model.

The design of communication protocol for controlling efficiently modular medical instruments (모듈화된 의료장비들의 효율적 제어를 위한 통신 프로토콜 설계)

  • 신창민;김영길
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2000.10a
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    • pp.284-287
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    • 2000
  • Recently, developing medical devices have a tendency becoming the module for satisfying user's mutual complex needs. Because the most effective method for the observation of patients condition a diagnosis and a treatment is collecting data from various devices and controling operation following it. Module tendency is more popular due to manage easily totally many individual systems. This study implemented communication protocol to control by one control system connecting modular medical devices. Implemented system consist of one master module controlling all module and managing communication and many Slave modules. Communication between each modules introduced SPI(Serial Peripheral Interface) among many synchronous serial communication methods for the exact transmission and receipt of data. All communication executes by packet format. This can detect error. And, this protocol introduced PNP(Plug And Play) function that auto-detect connecting or removing module during running. This protocol exactly transmitted and received in faster speed more than 1Mbps. And in practical application to the ventilator this confirmed to give and take real-time data. And various functions by th central control system is implemented in this protocol.

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A DLL-Based Multi-Clock Generator Having Fast-Relocking and Duty-Cycle Correction Scheme for Low Power and High Speed VLSIs (저전력 고속 VLSI를 위한 Fast-Relocking과 Duty-Cycle Correction 구조를 가지는 DLL 기반의 다중 클락 발생기)

  • Hwang Tae-Jin;Yeon Gyu-Sung;Jun Chi-Hoon;Wee Jae-Kyung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.2 s.332
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    • pp.23-30
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    • 2005
  • This paper describes a DLL(delay locked loop)-based multi-clock generator having the lower active stand-by power as well as a fast relocking after re-activating the DLL. for low power and high speed VLSI chip. It enables a frequency multiplication using frequency multiplier scheme and produces output clocks with 50:50 duty-ratio regardless of the duty-ratio of system clock. Also, digital control scheme using DAC enables a fast relocking operation after exiting a standby-mode of the clock system which was obtained by storing analog locking information as digital codes in a register block. Also, for a clock multiplication, it has a feed-forward duty correction scheme using multiphase and phase mixing corrects a duty-error of system clock without requiring additional time. In this paper, the proposed DLL-based multi-clock generator can provides a synchronous clock to an external clock for I/O data communications and multiple clocks of slow and high speed operations for various IPs. The proposed DLL-based multi-clock generator was designed by the area of $1796{\mu}m\times654{\mu}m$ using $0.35-{\mu}m$ CMOS process and has $75MHz\~550MHz$ lock-range and maximum multiplication frequency of 800 MHz below 20psec static skew at 2.3v supply voltage.

A New Clock Routing Algorithm for High Performance ICs (고성능 집적회로 설계를 위한 새로운 클락 배선)

  • 유광기;정정화
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.36C no.11
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    • pp.64-74
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    • 1999
  • A new clock skew optimization for clock routing using link-edge insertion is proposed in this paper. It satisfies the given skew bound and prevent the total wire length from increasing. As the clock skew is the major constraint for high speed synchronous ICs, it must be minimized in order to obtain high performance. But clock skew minimization can increase total wire length, therefore clock routing is performed within the given skew bound which can not induce the malfunction. Clock routing under the specified skew bound can decrease total wire length Not only total wire length and delay time minimization algorithm using merging point relocation method but also clock skew reduction algorithm using link-edge insertion technique between two nodes whose delay difference is large is proposed. The proposed algorithm construct a new clock routing topology which is generalized graph model while previous methods uses only tree-structured routing topology. A new cost function is designed in order to select two nodes which constitute link-edge. Using this cost function, delay difference or clock skew is reduced by connecting two nodes whose delay difference is large and distance difference is short. Furthermore, routing topology construction and wire sizing algorithm is developed to reduce clock delay. The proposed algorithm is implemented in C programming language. From the experimental results, we can get the delay reduction under the given skew bound.

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Effects of Synchronicity of Carbohydrate and Protein Degradation on Rumen Fermentation Characteristics and Microbial Protein Synthesis

  • Seo, J.K.;Kim, M.H.;Yang, J.Y.;Kim, H.J.;Lee, C.H.;Kim, K.H.;Ha, Jong K.
    • Asian-Australasian Journal of Animal Sciences
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    • v.26 no.3
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    • pp.358-365
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    • 2013
  • A series of in vitro studies were carried out to determine i) the effects of enzyme and formaldehyde treatment on the degradation characteristics of carbohydrate and protein sources and on the synchronicity of these processes, and ii) the effects of synchronizing carbohydrate and protein supply on rumen fermentation and microbial protein synthesis (MPS) in in vitro experiments. Untreated corn (C) and enzyme-treated corn (EC) were combined with soy bean meal with (ES) and without (S) enzyme treatment or formaldehyde treatment (FS). Six experimental feeds (CS, CES, CFS, ECS, ECES and ECFS) with different synchrony indices were prepared. Highly synchronous diets had the greatest dry matter (DM) digestibility when untreated corn was used. However, the degree of synchronicity did not influence DM digestibility when EC was mixed with various soybean meals. At time points of 12 h and 24 h of incubation, EC-containing diets showed lower ammonia-N concentrations than those of C-containing diets, irrespective of the degree of synchronicity, indicating that more efficient utilization of ammonia-N for MPS was achieved by ruminal microorganisms when EC was offered as a carbohydrate source. Within C-containing treatments, the purine base concentration increased as the diets were more synchronized. This effect was not observed when EC was offered. There were significant effects on VFA concentration of both C and S treatments and their interactions. Similar to purine concentrations, total VFA production and individual VFA concentration in the groups containing EC as an energy source was higher than those of other groups (CS, CES and CFS). The results of the present study suggested that the availability of energy or the protein source are the most limiting factors for rumen fermentation and MPS, rather than the degree of synchronicity.

MPSoC Design Space Exploration Based on Static Analysis of Process Network Model (프로세스 네트워크 모델의 정적 분석에 기반을 둔 다중 프로세서 시스템 온 칩 설계 공간 탐색)

  • Ahn, Yong-Jin;Choi, Ki-Young
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.10
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    • pp.7-16
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    • 2007
  • In this paper, we introduce a new design environment for efficient multiprocessor system-on-chip design space exploration. The design environment takes a process network model as input system specification. The process network model has been widely used for modeling signal processing applications because of its excellent modeling power. However, it has limitation in predictability, which could cause severe problem for real time systems. This paper proposes a new approach that enables static analysis of a process network model by converting it to a hierarchical synchronous dataflow model. For efficient design space exploration in the early design step, mapping application to target architectures has been a crucial part for finding better solution. In this paper, we propose an efficient mapping algorithm. Our mapping algorithm supports both single bus architecture and multiple bus architecture. In the experiments, we show that the automatic conversion approach of the process network model for static analysis is performed successfully for several signal processing applications, and show the effectiveness of our mapping algorithm by comparing it with previous approaches.

The Study for EV Charging Infrastructure connected with Microgrid (마이크로그리드와 연계된 전기자동차 충전인프라에 관한 연구)

  • Hun Shim
    • Journal of Internet of Things and Convergence
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    • v.10 no.1
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    • pp.1-6
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    • 2024
  • In order to increase the use of electric vehicles (EVs) and minimize grid strain, microgrid using renewable energy must take an important role. Microgrid may use fossil fuels such as small diesel power, but in many cases, they can be supplied with energy from renewable energy, which is an eco-friendly energy source. However, renewable energy such as solar and wind power have variable output characteristics. Therefore, in order to meet the charging and discharging energy demands of electric vehicles and at the same time supply load power stably, it is necessary to review the configuration of electric vehicle charging infrastructure that utilizes diesel power or electric vehicle-to-grid (V2G) as a parallel energy source in the microgrid. Against this background, this study modelized a microgrid that can stably supply power to loads using solar power, wind power, diesel power, and V2G. The proposed microgrid uses solar power and wind power generation as the primary supply energy source to respond to power demand, and determines the operation type of the load's electric vehicles and the rotation speed of the load synchronous machine to provide stable power from diesel power for insufficient generations. In order to verify the system performance of the proposed model, we studied the stable operation plan of the microgrid by simulating it with MATLAB /Simulink.