• 대한전기학회:학술대회논문집
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• 대한전기학회 1994년도 하계학술대회 논문집 C
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• pp.1223-1225
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• 1994

The properties of $TiN/TiSi_2$ bilayer formed by a rapid thermal anneal ing is investigated when thin $SiO_2$ film exists at the Ti-Si interface. The competitive reaction for the $TiN/TiSi_2$ bilayer occurs above $600^{\circ}C$. The thickness of the $TiSi_2$ layer decreases with increasing $SiO_2$ film thickness while the TiN layer increases at the competitive reaction. The composition of TiN layer is changed to the $TiN_xO_y$ film due to the thin $SiO_2$ layer at the Ti-Si interface while the structure of the TiN and $TiSi_2$ layers was not changed.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 하계학술대회 논문집
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• pp.71-74
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• 2000

Pt/Pb$TiO_3$/$SrTiO_3$/p-Si films were prepared by metallo-organic solution deposition(M0SD) method and investigated its structure and ferroelectric properties. Crystallinity of specimen as a funtions of post annealing temperature and the thickness of $SrTiO_3$(STO) buffer layer was studied using XRD and AFM. Based on C-V and P-E curve, $PbTiO_3$(PTO) capacitors showed good ferroelectric hysteresis arising from the polarization switching properties. When the thickness of ST0 buffer layer between PTO and Si substrate was 260 nrn and the post annealing temperature was $650^{\circ}C$, it was showed that production of the pyrochlore phase due to interdiffusion of Si into FTO was prevented. The dielectric constant of FTO thin films calculated from a maximum Cma in the accumulation region was 180 and the dielectric loss was 0.30 at 100 kHz frequency. The memory window in the C-V curve is 1.6V at a gate voltage of 5V.

• 한국재료학회지
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• 제4권2호
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• pp.143-151
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• 1994

$(PbZr_{52},Ti_{48})O_{3}$인 composite ceramic target을 사용하여 R. F. 마그네트론 스퍼터링 방법으로 기판온도 $300^{\circ}C$에서 Pt/Ti/Si 기판위에 PZT 박막을 증착하였다. 페롭스 카이트 PZT박막을 얻기 위하여 PbO분위기에서 로열처리를 행하였다. 하부전극으로 Pt를 사용하였으며 Pt(205$\AA$)/Ti(500 $\AA$)/Si 및 Pt(1000$\AA$)/Ti(500$\AA$)/Si기판을 준비하여 Pt두께화 Ti층이 산소의sink로 작용함으로서 이를 가속화하였다. Ti층의 상부는 산소의 확산으로 인하여 TiOx층으로 변태하였고 하부는 in diffused Pt와 함께 실리사이드층을 형성하였다. TiOx 층의 형성은PZT층의 방향성에 영향을 주었다. 유전상수 (10kHz), 누설전류, 파괴전압, 잔류분극 및 항전계는 각각 571, 32,65$\mu A /\textrm{cm}^2$, 0.40MV/cm, 3.3$\mu C /\textrm{cm}^2$, 0.15MV/cm이었다.

• 한국세라믹학회지
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• 제34권8호
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• pp.908-913
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• 1997

Multilayer NbCxC1-x/Y2O3/Ti were sputter-coated on the alumina substrate, starting with a 0.7 ㎛ thick NbCxC1-x layer grown on substrate, followed by 0.7 ㎛ thick Y2O3 layer and 1 ㎛ thick Ti layer. To find out the optimum conditions for thickness uniformity and adhesion, sputtering works have been done with the variation of sputtering power and Ar pressure. After vacuum annealing at 950℃ and 1000℃, the thermal stability of the NbCxC1-x/Y2O3/Ti coated alumina substrates has been investigated by peel off test. The coating scheme didn't cause any debonded layer after an annealing at 950℃ for 3hrs. However, it was peeled off after annealing at 1000℃ for 3hr. It was found that the thermal stability of Al2O3/NbCxC1-x/Y2O3/Ti coating scheme changed with the NbCxC1-x composition.

• 한국재료학회지
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• 제17권9호
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• pp.463-468
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• 2007

The interdiffusion characteristics of Cu-plug/Capping Layer/NiSi contacts were investigated. Capping layers were deposited on Ni/Si to form thermally-stable NiSi and then were utilized as diffusion barriers between Cu/NiSi contacts. Four different capping layers such as Ti, Ta, TiN, and TaN with varying thickness from 20 to 100 nm were employed. When Cu/NiSi contacts without barrier layers were furnace-annealed at $400^{\circ}C$ for 40 min., Cu diffused to the NiSi layer and formed $Cu_3Si$, and thus the NiSi layer was dissociated. But for Cu/Capping Layers/NiSi, the Cu diffusion was completely suppressed for all cases. But Ni was found to diffuse into the Cu layer to form the Cu-Ni(30at.%) solid solution, regardless of material and thickness of capping layers. The source of Ni was attributed to the unreacted Ni after the silicidation heat-treatment, and the excess Ni generated by the transformation of $Ni_2Si$ to NiSi during long furnace-annealing.

• 대한전기학회논문지
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• 제45권2호
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• pp.242-248
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• 1996

The properties of TiN/TiSi$_{2}$ bilayer formed by a rapid thermal annealing is investigated when thin SiO$_{2}$ film exists at the Ti-Si interface. The competitive reaction for the TiN/TiSi_2 bilayer occurs above 600 .deg. C. The thickness of the TiSi$_{2}$ layer decreases with increasing SiO$_{2}$ film thickness and also decreases with increasing anneal temperture When the competitive reaction for the TiN/TiSi$_{2}$ bilayer is occured by rapid thermal annealing, the composition of TiN layer represents TiN$_{x}$O$_{y}$ due to the SiO$_{2}$ layer at the Ti-Si interface but the structures of the TiN and TiSi$_{2}$ layers were not changed.d.d.

• 한국표면공학회지
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• 제15권4호
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• pp.208-217
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• 1982

To study the effect of TiC coating on weight change, microhardness, wear and heat - resistance of TiC layer, chemical vapour deposition on the various substrates has been carried out with the gaseous mixture of TiCl4, toluene, and H2 in the temperature range of 900 - 1000$^{\circ}C$. The results obtained are as follows ; (1) There is a limited value of carrier and reductant H2 gas flow rate, above which deteriorate effect on the TiC depoition arises (2) Increased thickness of TiC layer was resulted with increasing temperature and time. Better deposition was obtained with stainless steels and the best results were introduced by cobalt coating of substrates. (3) Wear resistance of the TiC coated specimen improved markedly. Heat resistivity of the coated steel showed excellent result, whereas the coated stainless Steels were infer-ior to the substrate.

• 공업화학
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• 제21권4호
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• pp.405-410
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• 2010

P25와 Dyesol $TiO_2$ (Titanium dioxide)를 사용하여 두께와 소성 온도가 다른 전극을 제조하여 염료감응형 태양전지(Dye Sensitized Solar Cell, DSSC)를 제조한 후 광 변환 효율을 측정하였다. 소성 전 후의 $TiO_2$ 작업 전극의 두께 변화는 FE-SEM을 사용하여 시편의 cross section을 확인하여 비교하였다. 또한 상대전극인 Pt의 소성 온도에 따른 DSSC의 효율 변화도 측정하였다. P25를 활용한 DSSC는 doctor blade로 1층으로 도포 후, $500^{\circ}C$에서 30 min 동안 소성한 작업 전극(${\sim}20.4{\mu}m$)과 $350^{\circ}C$에서 30 min 동안 소성한 Pt 상대 전극으로 제조한 셀이 3.8%의 광효율을 나타내었다. Dyesol $TiO_2$를 활용하여 1층으로 도포 후, $500^{\circ}C$에서 30 min 동안 소성한 작업전극(${\sim}9.1\;{\mu}m$)과 $450^{\circ}C$에서 30 min 동안 소성한 Pt 상대 전극으로 제조한 셀이 5.8%의 광 효율을 나타냄을 알았다.

• 한국산학기술학회논문지
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• 제6권3호
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• pp.270-272
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• 2005

코발트 실리사이드는 낮은 전기 저항성 때문에 고효율 소자를 제조하는데 적합한 물질이다. 이는 전자소재가 소형화되면서 접촉저항과 혼합을 줄이기 위해 더욱 필요하게 되었다. 본 연구에서는 티타늄의 표면산화에 미치는 영향과, RTO 조건에서 온도에 따른 코발트 실리사이드 박막의 산화정도를 측정했다. 기질로서 p-형 실리콘웨이퍼를 사용하였고, 고속 열 가공을 통하여 박막을 가공하였다. 티타늄 층을 입혔을 때 산화충의 두께는 $500{\AA}$정도 성장하였다. 고속 열산화의 온도변화에 따라 산화막은 $550^{\circ}C\~700^{\circ}C$까지는 성장을 보였으나 $700^{\circ}C$이상에는 산화막 성장이 포화상태를 보였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 추계학술대회 논문집 전기물성,응용부문
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• pp.183-186
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• 2004

The metal-ferroelectric-insulator-semiconductor(MFIS) capacitors were fabricated using a metalorganic decomposition (MOD)method. The $CeO_2$ thin films were deposited as a buffer layer on Si substrate and $Bi_{3.25}La_{0.75}Ti_3O_{12}$ (BLT) thin films were used as a ferroelectric layer. The electrical and structural properties of the MFIS structure were investigated by varying the $CeO_2$ layer thickness. The width of the memory window in the capacitance-voltage (C-V)curves for the MFIS structure decreased with increasing thickness of the $CeO_2$ layer. Auger electron spectroscopy (AES) and transmission electron microscopy (TEM) show no interdiffusion by using the $CeO_2$ film as buffer layer between the BLT film and Si substrate. The experimental results show that the BLT-based MFIS structure is suitable for non-volatile memory field-effect-transistors (FETs) with large memory window.