• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.3-3
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• 2010

We investigated the influence of the indium content on the threshold voltage ($V_{th}$) shift of sol-gel-derived indium-gallium-zinc oxide (IGZO) thin film transistors (TFTs). Surplus indium composition ratio into IGZO decreases the value of $V_{th}$ of IGZO TFTs showed huge $V_{th}$ shift in the negative direction. $V_{th}$ shift decreases from 10 to -28.2V as Indium composition ratio is increased. Because the free electron density is increased according to variation of the Indium composition ratio.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권2호
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• pp.1673-1676
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• 2007

We have investigated the degradation mechanism of hydrogenated amorphous silicon (a- Si:H) thin film transistors (TFTs) The threshold voltage of driving a-Si:H TFT is shifted severely by electrical bias due to a charge trapping and defect state creation. And the short channel TFTs exhibit less threshold voltage degradation than long channel TFTs. We propose the pixel circuits employing negative bias annealing scheme in order to suppression of threshold voltage shift of a-Si:H TFT.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.1243-1246
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• 2009

A novel a-Si TFT integrated gate driver circuit which suppresses the threshold voltage shift due to prolonged positive gate bias to pull-down TFTs, is reported. Negative gate-to-drain bias is applied alternately to the pull-down TFTs to recover the threshold voltage shift. Consequently, the stability of the circuit has been improved considerably.

• 대한전자공학회논문지
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• 제24권3호
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• pp.459-465
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• 1987

This paper describes the circuit and the layout of the shift register which can be used for a scanner of image sensor. P-well concentration and threshold voltage for proper iperation are calculated on the basso of the fixed process and the layout design. The calculation procedure of maximum operation frequency is also carried out. It is ascertained by SPICE simulation that the shift register produces the outputn pulse without threshold voltage loss up to 13MHz.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2005년도 춘계종합학술대회
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• pp.981-984
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• 2005

본 논문에서는 전하트랩형 SONOS 메모리에서 프로그래밍 동작 후 변화되는 문턱전압을 시뮬레이션에 의하여 구현하고자 한다. SONOS 소자는 질화막내의 트랩 뿐 만아니라, 질화막-블로킹산화막 계면에 존재하는 트랩에 전하를 저장하는 전하트랩형 비휘발성기억소자로서, 기억상태에 따른 문턱전압을 시뮬레이션으로 구현하기위해서는 질화막내의 트랩을 정의할 수 있어야 된다. 그러나 기존의 시뮬레이터에서는 질화막내의 트랩모델이 개발되어 있지 않은 것이 현실이다. 따라서 본 연구에서는 SONOS 구조의 터널링산화막-질화막 계면과 질화막-블로킹산화막 계면에 두개의 전극을 정의하여 프로그램 전압과 시간에 따라서 전극에 유기되는 전하량으로부터 전하트랩형 기억소자의 문턱전압변화를 시뮬레이션 할 수 있는 새로운 방법을 제안한다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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• pp.322-325
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• 2000

N-channel poly-Si TFT, Processed by Solid Phase Crystalline(SPC) on a glass substrate, has been investigated by measuring its electrical properties before and after electrical stressing. It is observed that the threshold voltage shift due to electrical stress varies with various stress conditions. Threshold voltages measured in 1.5$\mu\textrm{m}$ and 3$\mu\textrm{m}$ poly-Si TFTs are 3.3V, 3.V respectively. With the threshold voltage shia the degradation of transconductance(G$\_$m/) and subthreshold swing(S) is also observed.

• 반도체디스플레이기술학회지
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• 제20권4호
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• pp.141-145
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• 2021

The brightness of the Organic Light Emitting Diode (OLED) display is controlled by thin-film transistors (TFTs). Regardless of the materials and the structures of TFTs, an OLED suffers from the instable threshold voltage (V_th) of a TFT during operation. When designing an OLED pixel with circuit simulation tool such as SPICE, a designer needs to take V_th shift into account to improve the reliability of the circuit and various compensation methods have been proposed. In this paper, the effect of the compensation circuits from two typical OLED pixel circuits proposed in the literature are studied by the transient simulation with a SPICE tool in which the stretched-exponential time dependent V_th shift function is implemented. The simulation results show that the compensation circuits improve the reliability at the beginning of each frame, but V_th shifts from all TFTs in a pixel need to be considered to improve long-time reliability.

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권2호
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• pp.83-88
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• 2003

The reset operation of a CCD image sensor was improved using charge trapping of a MOS structure to realize a loe voltage driving. A DC bias generating circuit was added to the reset structure which sets reference voltage and holds the signal charge to be detected. The generated DC bias is added to the reset pulse to give an optimized voltage margin to the reset operation, and is controlled by adjustment of the threshold voltage of a MOS transistor in the circuit. By the pulse-type stress voltage applied to the gate, the electrons and holes were injected to the gate dielectrics, and the threshold voltage could be adjusted ranging from 0.2V to 5.5V, which is suitable for controlling the incomplete reset operation due to the process variation. The charges trapped in the silicon nitride lead to the positive and negative shift of the threshold voltage, and this phenomenon is explained by Poole-Frenkel conduction and Fowler-Nordheim conduction. A CCD image sensor with $492(H){\;}{\times}{\;}510(V)$ pixels adopting this structure showed complete reset operation with the driving voltage of 3.0V. The resolution chart taken with the image sensor shows no image flow to the illumination of 30 lux, even in the driving voltage of 3.0V.

• 대한전자공학회논문지SD
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• 제47권10호
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• pp.1-6
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• 2010

본 연구에서는 S-파라미터 측정 데이터를 사용하는 RF측정방법으로 short-channel MOSFET의 RF 캐패시턴스 전압(C-V) 곡선을 상온에서 $225^{\circ}C$까지 추출하였으며, 추출된 고온 종속 특성을 엠피리컬하게 모델링하였다. RF C-V 특성곡선의 weak inversion영역에서 온도 변화에 따른 voltage shift가 threshold voltage shift보다 적은 현상이 관찰되었지만, 기존 long-channel C-V 이론 방정식으로 설명할 수 없는 현상임이 입증되었다. 이러한 short-channel C-V 곡선의 고온 종속 모델링을 위해서 새로운 엠피리컬 방정식이 개발되었다. 이 방정식의 정확도는 모델된 C-V곡선과 측정 데이터가 넓은 온도범위에서 잘 일치하는 결과를 관찰함으로써 입증되었다. 또한, 높은 게이트 전압에서는 온도가 증가함에 따라 채널 캐패시턴스 값이 감소하는 것을 확인할 수 있다.

• 전자공학회논문지A
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• 제28A권9호
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• pp.736-742
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• 1991

N$^{+}$poly gate NMOSFETs and p$^{+}$ poly gate (surface type) PMOSFETs with three different gate oxides(SiO2, NO, and ONO) were fabricated. The rapid thermal nitridation and reoxidation techniques have been applied to gate oxide formation. The current drivability of the ONO NMOSFET shows larger values than that of the SiO2 NMOSFET. The snap-back occurs at a lower drain voltage for SiO$_2$ cases for ONO NMOSFET. Under the maximum substrate current bias conditions, hot-carrier effects inducting threshold voltage shift and transconductance degradation were investigated. The results indicate that ONO films exhibit less degradation in terms of threshold voltage shift. It was confirmed that the ONO samples achieve good improvement of hot-carrier immunity. In a SiO$_2$ SC-PMOSFET, with significant boron penetration, it becomes a depletion type (normally-on). But ONO films show excellent impurity barrier properties to boron penetration from the gate.