• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.3
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• pp.166-173
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• 2009

The reliability of hafnium oxide gate dielectrics incorporating lanthanum (La) is investigated. nMOSFETs with metal/La-doped high-k dielectric stack show lower $V_{th}$ and $I_{gate}$, which is attributed to the dipole formation at the high-k/$SiO_2$ interface. The reliability results well correlate with the dipole model. Due to lower trapping efficiency, the La-doping of the high-k gate stacks can provide better PBTI immunity, as well as lower charge trapping compared to the control HfSiO stacks. While the devices with La show better immunity to positive bias temperature instability (PBTI) under normal operating conditions, the threshold voltage shift (${\Delta}V_{th}$) at high field PBTI is significant. The results of a transconductance shift (${\Delta}G_m$) that traps are easily generated during high field stress because the La weakens atomic bonding in the interface layer.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.7
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• pp.569-574
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• 2007

In this paper, the reliability (NBTI degradation: ${\Delta}V_{th}$) and device characteristic of nano-scale PMOSFET with plasma nitrided oxide (PNO) is characterized in depth by comparing those with thermally nitrided oxide (TNO). PNO case shows the reduction of gate leakage current and interface state density compared to TNO with no change of the $I_{D.sat}\;vs.\;I_{OFF}$ characteristics. Gate oxide capacitance (Cox) of PNO is larger than TNO and it increases as the N concentration increases in PNO. PNO also shows the improvement of NBTI characteristics because the nitrogen peak layer is located near the $Poly/SiO_2$ interface. However, if the nitrogen concentration in PNO oxide increases, threshold voltage degradation $({\Delta}V_{th})$ becomes more degraded by NBT stress due to the enhanced generation of the fixed oxide charges.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.211.1-211.1
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• 2015

최근 용액 공정을 이용한 산화물 반도체에 대한 연구가 활발히 진행되고 있다. 넓은 밴드갭을 가지고 있는 산화물 반도체는 높은 투과율을 가지고 있어 투명 디스플레이에 적용이 가능하다. 기존의 박막 진공증착 방법은 진공상태를 유지하기 위한 장비의 가격이 비싸며, 대면적의 어려움, 높은 생산단가 등으로 생산율이 높지 않다. 하지만 용액 공정을 이용하면 대기압에서 증착이 가능하고 대면적화가 가능하다. 그리고 각각의 조성비를 조절하는 것이 가능하다. 이러한 장점에도 불구하고, 소자의 신뢰성이나 저온공정은 중요한 이슈이다. Instability는 threshold voltage (Vth)의 shift 및 on/off switching의 신뢰성과 관련된 parameter이다. 용액은 소자의 전기적 특성을 열화 시키는 수분 과 탄소계열의 불순물을 다량 포함 하고 있어 고품질의 박막을 형성하기 위해서는 고온의 열처리가 필요하다. 기존의 열처리는 고온에서 장시간 이루어지기 때문에 유리나 플라스틱, 종이 기판의 소자에서는 불가능하지만 $100^{\circ}C$ 이하의 저온 공정인 microwave를 이용하면 유리, 플라스틱, 종이 기판에서도 적용이 가능하다. 본 연구에서는 산화물 반도체 중에서 InGaZnO (IGZO)를 용액 공정으로 제작한 juctionless thin-film transistor를 제작하여 기존의 열처리를 이용하여 처리한 소자와 microwave를 이용해서 열처리한 소자의 전기적 특성을 한 달 동안 관찰 하였다. 또한 In:Zn의 비율을 고정한 후 Ga의 비율을 달리하여 특성을 비교하였다. 먼저 p-type bulk silicon 위에 SiO2 산화막이 100 nm 증착된 기판에 RCA 클리닝을 진행 하였고, solution InGaZnO 용액을 spin coating 방식으로 증착하였다. Coating 후에, solvent와 수분을 제거하기 위해서 $180^{\circ}C$에서 10분 동안 baking공정을 하였다. 이후 furnace열처리와 microwave열처리를 비교하기 위해 post-deposition-annealing (PDA)으로 furnace N2 분위기에서 $600^{\circ}C$에서 30분, microwave를 1800 W로 2분 동안 각각의 샘플에 진행하였다. 또한, HP 4156B semiconductor parameter analyzer를 이용하여 제작된 TFT의 transfer curve를 측정하였다. 그 결과, microwave 열처리한 소자의 경우 기존의 furnace 열처리 소자와 비교하여 높은 mobility, 낮은 hysteresis 값을 나타내었으며, 1달간 소자의 특성을 관찰하였을 때 microwave 열처리한 소자의 경우 전기적 특성이 거의 변하지 않는 것을 확인하였다. 따라서 향후 용액공정, 저온공정을 요구하는 소자 공정에 있어 열처리방법으로 microwave를 이용한 활용이 기대된다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.2
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• pp.348-354
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• 2009

It has analyzed that the device degradation by NBTI (Negative Bias Temperature Instability) stress induced the increase of gate-induced-drain-leakage(GIDL) current for p-MOSFETs. It is shown that the degradation magnitude, as well as its time, temperature, and field dependence, is govern by interface traps density at the silicon/oxide interface. from the relation between the variation of threshold voltage and subthreshold slope, it has been found that the dominant mechanism for device degradation is the interface state generation. From the GIDL measurement results, we confined that the EHP generation in interface state due to NBTI stress led to the increase of GIDL current. Therefore, one should take care of the increased GIDL current after NBTI stress in the ultra-thin gate oxide device. Also, the simultaneous consideration of reliability characteristics and dc device performance is highly necessary in the stress engineering of nanoscale CMOSFETs.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.1A
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• pp.80-86
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• 2010

This work has been measured and analyzed the device degradation of NBTI (Negative Bias Temperature Instability) stress induced the increase of gate-induced-drain-leakage(GIDL) current for p-MOS transistors of gate channel length 0.13 [${\mu}m$]. From the relation between the variation of threshold voltage and subthreshold slop by NBTI stress, it has been found that the dominant mechanism for device degradation is the interface state generation. From the GIDL measurement results, we confined that the EHP generation in interface state due to NBTI stress led to the increase of GIDL current. As a results, one should take care of the increased GIDL current after NBTI stress in the ultra-thin gate oxide device. Also, the simultaneous consideration of reliability characteristics and dc device performance is highly necessary in the stress parameters of nanoscale CMOS communication circuit design.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.3
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• pp.182-187
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• 2011

In this paper, PBTI characteristics of NMOSFETs with La incorporated HfSiON and HfON are compared in detail. The charge trapping model shows that threshold voltage shift (${\Delta}V_{\mathrm{T}}$) of NMOSFETs with HfLaON is greater than that of HfLaSiON. PBTI lifetime of HfLaSiON is also greater than that of HfLaON by about 2~3 orders of magnitude. Therefore, high charge trapping rate of HfLaON can be explained by higher trap density than HfLaSiON. The different de-trapping behavior under recovery stress can be explained by the stable energy for U-trap model, which is related to trap energy level at zero electric field in high-k dielectric. The trap energy level of two devices at zero electric field, which is extracted using Frenkel-poole emission model, is 1,658 eV for HfLaSiON and 1,730 eV for HfLaON, respectively. Moreover, the optical phonon energy of HfLaON extracted from the thermally activated gate current is greater than that of HfLaSiON.