• Journal of Electrical Engineering and Technology
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• v.10 no.2
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• pp.586-594
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• 2015

This paper proposes a maximum efficiency operation strategy for three-level T-type inverter in entire operation areas. The three-level T-type inverter has higher and lower efficiency areas compared with two-level inverter. The proposed strategy aims to operate in the maximum efficiency point for the low-voltage and low-power home appliances. The three-level T-type inverter is analyzed in detail, and the two operation mode selection strategy is developed. The proposed algorithm is verified by theoretical analysis and experimental results.

• Journal of Power Electronics
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• v.9 no.3
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• pp.481-490
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• 2009

This paper describes a SVPWM overmodulation scheme of NPC type three-level inverter for traction drives which extends the modulation index from MI=0.907 to unity. SVPWM strategy is organized by two operation modes of under-modulation and over-modulation. The switching states under the under-modulation modes are determined by dividing them with two linear regions and one hybrid region the same as the conventional three-level inverter. On the other hand, under the over-modulation mode, they are generated by doing it with two over-modulation regions the same as the conventional over-modulation strategy of a two level inverter. Following the description of over-modulation scheme of a three-level inverter, the system description of a vector controlled induction motor for traction drives has been discussed. Finally, the validity of the proposed modulation algorithm has been verified through simulation and experimental results.

• Journal of Power Electronics
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• v.15 no.6
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• pp.1517-1523
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• 2015

The wavelet PWM (WPWM) technique has been applied in two-level inverters successfully, but directly applying the WPWM technique to three-level inverters is impossible. This paper proposes a WPWM technique suitable for a single-phase three-level inverter. The work analyzes the control strategy with the WPWM and obtains the design of its parameters. Compared with the SPWM technique for a single-phase three-level inverter under the same conditions, the WPWM can obtain high magnitudes of the output fundamental frequency component, low total harmonic distortion, and simpler digital implementation. The feasibility experiment is given to verify of the proposed WPWM technique.

• Proceedings of the KSME Conference
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• 2008.11b
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• pp.2401-2405
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• 2008

In the present study, a three-dimensional least square/level set based two-phase flow code was developed for the simulation of three-dimensional sloshing problems using finite element discretization. The present method can be utilized for the analysis of a free surface flow problem in a complex geometry due to the feature of FEM. Since the finite element method is employed for the spatial discretization of governing equations, an unstructured mesh can be naturally adopted for the level set simulation of a free surface flow without an additional load for the code development except that solution methods of the hyperbolic type redistancing and advection equations of the level set function should be devised in order to give a bounded solution on the unstructured mesh. From the numerical experiments of the present study, it is shown that the proposed method is both robust and accurate for the simulation of three-dimensional sloshing problems.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.45 no.4
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• pp.535-542
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• 1996

A zero voltage switching (ZVS) three level auxiliary resonant commutated pole inverter (ARCPI) is presented for high power GTO inverters. The concept of ARCP for two level inverter is extended to the three inverter. The proposed auxiliary commutation circuit consists of one resonant inductor and two bi-directional switches, which provides ZVS condition to the main devices without increasing device voltage or current stresses. The auxiliary device operates with zero current switching (ZCS) which enables use of the low cost thyristors. The proposed ARCPI can handle higher voltage and higher power (1-10MVA) comparing to the two level one. Operation and analysis of the ARCPI are illustrated and the features are compared o those of the snubber circuit incorporated three level inverter. Experimental results with 10kW, 4kHz prototype are presented to verify the principle of operation. (author). refs., figs., tab.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.2
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• pp.319-328
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• 2016

This paper proposes a simplified SVPWM for three level inverters in transformerless photovoltaic (PV) systems. With the proposed SVPWM the three level space vector (SV) diagram is divided into only six sectors as in conventional two level SV diagram in such a way that only seven SVs are used among all the available SVs of three level inverter. The main features of the proposed SVPWM are that it is simple to implement, less switching losses as compared to conventional SVPWM and most importantly it eliminates the leakage currents in transformerless PV systems. Detailed theoretical analysis of the proposed SVPWM are presented and verified by numerical simulations and experimental results.

• Journal of Electrical Engineering and Technology
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• v.9 no.2
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• pp.489-500
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• 2014

This paper presents a simple modified unipolar carrier-based pulsewidth modulation (CB-PWM) strategy for the three-level neutral-point-clamped (NPC) voltage source inverter (VSI). Analytical expressions for the relationship between modulation reference signals and output voltages are derived. The proposed modulation technique for the three-level NPC VSI includes the maximum and minimum of the three-phase sinusoidal reference voltages with zero-sequence voltage injection concept. The proposed modified CB-PWM strategy incorporates a novel method that requires only of one triangular carrier wave for generate the gating pulses in three-level NPC VSI. It has the advantages of being simplifying the algorithm with no need of complex two/multi-carrier pulsewidth modulation or space vector modulation (SVM) and it's also simple to implement. The possibility of the proposed CB-PWM technique has been verified though computer simulation and experimental results.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.384-387
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• 2000

In this paper Power factor correction circuit of single-phase three-level boost converter is proposed. The advantage of the proposed control scheme for three-level boost converter are low blocking voltage of each power device low THD(Total Harmonic Distortion) and high power factor. The control scheme is based on the current comparator capacitor compensator and region detector, In simulations the proposed system is validated.

• Journal of Power Electronics
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• v.16 no.6
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• pp.2162-2172
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• 2016

This paper presents a Direct Torque Control (DTC) strategy for the five-phase induction motor driven by a three-level five-phase inverter in order to improve the performance of the five-phase induction motor. In the proposed DTC technique, only 22 voltage vectors out of 243 available voltage vectors in a three-level five-phase inverter are selected and are divided in 10 sectors each with a width of $36^{\circ}$. The four different DTC combinations (DTC-I, II, III and IV) for a three-level five-phase induction motor drive are investigated for improving the performance of five-phase induction motor. All four of the DTC strategies utilize a combination of the same large and zero voltage vectors, but with different medium voltage vectors. Out of these four techniques, DTC-II gives the best performance when compared to the others. This DTC-II technique is analyzed in detail for improvements in the performance of five-phase induction motor in terms of torque ripple, x-y stator flux and Total Harmonics Distortion (THD) of the stator phase current when compared to its two-level counterparts. To verify the effectiveness of the proposed three-level five-phase DTC control strategy, a DSP based experimental system is build. Simulation and experimental results are provided in order to validate the proposed DTC technique.

• Journal of Electrical Engineering and Technology
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• v.10 no.1
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• pp.128-137
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• 2015

A novel parallel three-level zero voltage switching (ZVS) DC converter is presented for medium voltage applications. The proposed converter includes three sub-circuits connected in parallel with the same power switches to share load current and reduce the current stress of passive components at the output side. Thus, the size of the output chokes is reduced and the switch counts in the proposed converter are less that in the conventional parallel three-level DC/DC converter. Each sub-circuit combines one half-bridge converter and one three-level converter. The transformer secondary windings of these two converters are connected in series in order to reduce the size of output inductor. Due to the three-level circuit topology, the voltage stress of power switches is equal to $V_{in}/2$. Based on the resonant behavior by the output capacitance of power switches and the leakage inductance (or external inductance) at the transition interval, each switch can be turned on under ZVS. Finally, experiments based on a 2 kW prototype are provided to verify the performance of the proposed converter.