• Journal of Power Electronics
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• v.16 no.4
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• pp.1513-1525
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• 2016

Rapid and accurate phase synchronization is critical for the reliable control of grid-tied inverters. However, the commonly used software phase-locked loop methods do not always satisfy the need for high-speed and accurate phase synchronization under severe grid imbalance conditions. To address this problem, this study develops a novel open-loop phase locking scheme based on a synchronous reference frame. The proposed scheme is characterized by remarkable response speed, high accuracy, and easy implementation. It comprises three functional cascaded blocks: fast orthogonal signal generation block, fast fundamental-frequency positive sequence component construction block, and fast phase calculation block. The developed virtual orthogonal signal generation method in the first block, which is characterized by noise immunity and high accuracy, can effectively avoid approximation errors and noise amplification in a wide range of sampling frequencies. In the second block, which is the foundation for achieving fast phase synchronization within 3 ms, the fundamental-frequency positive sequence components of unsymmetrical grid voltages can be achieved with the developed orthogonal signal construction strategy and the symmetrical component method. The real-time grid phase can be consequently obtained in the third block, which is free from self-tuning closed-loop control and thus improves the dynamic performance of the proposed scheme. The proposed scheme is adaptive to severe unsymmetrical grid voltages with sudden changes in magnitude, phase, and/or frequency. Moreover, this scheme is able to eliminate phase errors induced by harmonics and random noise. The validity and utility of the proposed scheme are verified by the experimental results.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.1
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• pp.197-204
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• 2010

This paper proposes a new body-effect compensated switch configuration for low voltage and low distortion switched-capacitor (SC) applications. The proposed circuit allows rail-to-rail switching operation for low voltage SC circuits and has better total harmonic distortion than the conventional bootstrapped circuit by 19 dB. A 2-1 cascaded sigma-delta modulator is provided for performing the high-resolution analog-to-digital conversion on audio codec in a communication transceiver. An experimental prototype for a single-stage folded-cascode operational amplifier (opamp) and a 2-1 cascaded sigma-delta modulator has been implemented m a 0.25 micron double-poly, triple-metal standard CMOS process with 2.7 V of supply voltage. The 1% settling time of the opamp is measured to be 560 ns with load capacitance of 16 pF. The experimental testing of the sigma-delta modulator with bit-stream inspection and analog spectrum analyzing plot is performed. The die size is $1.9{\times}1.5\;mm$.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.2
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• pp.56-61
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• 2010

In this paper, high efficient power amplifier with dual band has been realized. Dual band power amplifier have used modify stub matching for single FET, center frequency 2.14GHz and 5.2GHz respectively. The dual-band operation of the CRLH TL is achieved by the frequency offset and the nonlinear phase slope of the CRLH TL for the matching network of the power amplifier. Because the control of the all harmonic components is very difficult m dual-band, we have managed only the second- and third-harmonics to obtain the high efficiency with the CRLH TL in dual-band. Dual-band characteristics in the output has to balance. Two operating frequencies are chosen at 2.14 GHz and 5.2 GHz in this work. The measured results show that the output power of 28.56 dBm and 29 dBm was obtained at 2.14 GHz and 5.2 GHz, respectively. At this point, we have obtained the power-added efficiency (PAE) of 65.824 % and 69.86 % at two operation frequencies, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.8 s.111
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• pp.725-731
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• 2006

A novel design of frequency multiplier using a feedforward technique and a defected ground structure(DGS) is proposed. The feedforward loop in the proposed frequency multiplier suppresses the fundamental component $(f_0)$, the dumb-bell or spiral shaped DGS diminish unwanted harmonics such as second, third and fourth. Due to the combination of the feedforward structure and the DGS, only the multiplied frequency component$(2f_0,\;3f_0,\;4f_0)$ appears at the output port and the other unwanted components are suppressed excellently. The frequency multiplier is designed at 1 GHz $(f_0)$, by the proposed technique and measured. The measured output power of $2f_0,\;3f_0$ and $4f_0$ is -2.59 dBm, -5.36dBm and -4.57dBm, respectively, when the input power is 0dBm.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.2
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• pp.107-113
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• 2008

This paper presents half wavelength partial H-plane filters with multiple attenuation poles using narrow H-plane slot of evanescent waveguide. The narrow H-plane slot operates as an admittance inverter o( the bandpass filter and, simultaneously, generates an attenuation pole at particular frequency. Therefore, proposed filters with attenuation poles are simply implemented without any additional coupling and extra modification of the structure. The number of attenuation poles of the filters equals to that of the H-plane slots. Moreover, proposed filters are compact waveguide filter since ones are embodied by partial H-plane waveguide which has 1/4 cross section of conventional waveguide. The third and fourth-order half wavelength filters having 4 and 5 attenuation poles, respectively, are designed in H-band and their frequency responses are confirmed by simulation and measurement.

• Journal of the Korean Society for Precision Engineering
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• v.22 no.8 s.173
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• pp.165-173
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• 2005

This paper presents the results for deposition of micrometer-scale metal lines on glass for the development of TFT-LCD circuit repair-system. Although there had been a few studies in the late 1980's for the deposition of metallic interconnects by laser-induced chemical vapor deposition, those studies mostly used continuous wave lasers. In this work, a third harmonic Nd:YLF laser (351nm) of high repetition rates, up to 10 KHz, was used as the illumination source and W(CO)s was selected as the precursor. General characteristics of the metal deposit (tungsten) such as height, width, morphology as well as electrical properties were examined for various process conditions. Height of the deposited tungsten lines ranged from 35 to 500 m depending on laser power and scan speed while the width was controlled between 50um using a slit placed in the beam path. The resistivity of the deposited tungsten lines was measured to be below $1{\Omega}{\cdotu}um$, which is an acceptable value according to the manufacturing standard. The tungsten lines produced at high scan speed had good surface morphology with little particles around the patterns. Experimental results demonstrated that it is likely that the deposit forms through a hybrid process, namely through the combination of photolytic and pyrolytic mechanisms.

• Journal of the Korean Home Economics Association
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• v.47 no.1
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• pp.45-54
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• 2009

The purpose of the study is to examine the characteristics of the ideal housing for the modern family suggested by the Home Exposition (September, 1915) under the Japanese colonial rule in the macroscopic context of social change and the microscopic context of family. Through this research, we expect to have a partial understanding not only of changes in the outward appearance of traditional housing spaces during the civilization period and the early Japanese colonial rule when foreign cultures began to be introduced but also of families'residential lives and the patterns of change in people's consciousness of housing. Major conclusions from the current analysis are as follows. First, there were some changes in family paradigm induced through a home exhibition. Second, the most important factor for an ideal housing was that it must be the source of harmonic and healthy family life. Third, the importance of an appropriate space norm should be emphasized by providing the minimum size of each room. Fourth, the significance of the housing values of the economy, convenience, and hygiene should be emphasized for the ideal housing. Lastly, it was implied that for an ideal housing, the social and psychological aspects of housing must be satisfied along with the physical aspects. The limitation was that the model of ideal family housing presented in the Home Exposition cannot exclude the characteristics of the colonial perspectives in that it was followed by the model for the Japanese families.

• Journal of Power Electronics
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• v.18 no.3
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• pp.702-713
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• 2018

Power loss reduction and total harmonic distortion(THD) minimization are two important goals of improving three-level inverters. In this paper, an optimized pulse width modulation (PWM) strategy that can reduce switching losses and balance the neutral point with an optional THD of three-level neutral-point-clamped inverters is proposed. An analysis of the two-level discontinuous PWM (DPWM) strategy indicates that the optimal goal of the proposed PWM strategy is to reduce switching losses to a minimum without increasing the THD compared to that of traditional SVPWMs. Thus, the analysis of the two-level DPWM strategy is introduced. Through the rational allocation of the zero vector, only two-phase switching devices are active in each sector, and their switching losses can be reduced by one-third compared with those of traditional PWM strategies. A detailed analysis of the impact of small vectors, which correspond to different zero vectors, on the neutral-point potential is conducted, and a hysteresis control method is proposed to balance the neutral point. This method is simple, does not judge the direction of midpoint currents, and can adjust the switching times of devices and the fluctuation of the neutral-point potential by changing the hysteresis loop width. Simulation and experimental results prove the effectiveness and feasibility of the proposed strategy.

• Journal of the Korean Society for Nondestructive Testing
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• v.33 no.1
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• pp.14-19
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• 2013

Nonlinearity parameter is an inherent property of materials measuring fundamental acoustic amplitude($A_1$) and second harmonic amplitude($A_2$). However, measurement of $A_1$ and $A_2$ has complex calibration procedure, many researchers prefer to measure relative nonlinearity parameter rather than absolute nonlinearity parameter. But, relative nonlinearity parameter is only detect materials degradation with various degradation samples, it is limited application in determining third order elastic constants of materials. Therefore, in this study, the piezoelectric detection method is adopted to measure absolute nonlinearity parameter due to experimental simplicity compare to capacitive detector. Linearity of measurement system is verified by $A_1^2vsA_2$ plot, and we measured ultrasonic nonlinearity parameters of fused silica and Al2024-T4.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.12
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• pp.78-83
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• 2010

In this paper, a novel dual-band power amplifier using metamaterials has been realized with one RF GaN HEMT diffusion metal-oxide-semiconductor field effect transistor. The CRLH TL can lead to metamaterial transmission line with the dual-band tuning capability. The dual-band operation of the CRLH TL is achieved by the frequency offset and the nonlinear phase slope of the CRLH TL for the matching network of the power amplifier. We have managed only the second- and third-harmonics to obtain the high efficiency with the CRLH TL in dual-band. Also, the proposed power amplifier has been realized by using the harmonic control circuit for not only the output matching network, but also the input matching network for better efficiency. Two operating frequencies are chosen at 900 MHz and 2140 MHz in this work. The measured results show that the output power of 39.83 dBm and 35.17 dBm was obtained at 900 MHz and 2140 MHz, respectively. At this point, we have obtained the power-added efficiency (PAE) and IMD of 60.2 %, -23.17dBc and 67.3 %, -25.67dBc at two operation frequencies, respectively.