• Journal of the Microelectronics and Packaging Society
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• v.23 no.1
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• pp.17-22
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• 2016

Flexible organic light-emitting diode (OLED) devices consist of multi-stacked thin films or layers comprising organic and inorganic materials. Due to thermal coefficient mismatch of the multi-layer films, warpage of the flexible OLED is generated during high temperature process of each layer. This warpage will create the critical issues for next production process, consequently lowering the production yield and reliability of the flexible OLED. In this study, we investigate the warpage behavior of the flexible OLED for each bonding process step of the multi-layer films using the experimental and numerical analysis. It is found that the polarizer film and barrier film show significant impact on warpage of flexible OLED, while the impact of the OCA film on warpage is negligible. The material that has the most dominant impact on the warpage is a plastic cover. In order to minimize the warpage of the flexible OLED, we estimate the optimal material properties of the plastic cover using design of experiment. It is found that the warpage of the flexible OLED is reduced to less than 1 mm using a cover plastic of optimized properties which are the elastic modulus of 4.2 GPa and thermal expansion coefficient of $20ppm/^{\circ}C$.

• Journal of Mechanical Science and Technology
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• v.14 no.2
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• pp.251-258
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• 2000

Thermal deformation in an electronic package due to thermal strain mismatch is investigated. The warpage and the in-plane deformation of the package after encapsulation is analyzed using the laminated plate theory. An exact solution for the thermal deformation of an electronic package with circular shape is derived. Theoretical results are presented on the effects of the layer geometries and material properties on the thermal deformation. Several applications of the exact solution to electronic packaging product development are illustrated. The applications include lead on chip package, encapsulated chip on board and chip on substrate.

• Journal of the Korean Society of Industry Convergence
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• v.14 no.3
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• pp.87-93
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• 2011

When applying back panel(this material is aluminum complex panel coated with fire resistance substances) for curtain wall, solar radiation and heat storage of indoor air occurs to result in thermal warpage for back panel. The purpose of this analysis is to find out the cause of thermal warpage and come up with a solution to prevent changes of back panel and reduce elements that bring negative visual elements. Also to solve this problem analyse that case to reduce heat transfer by inserting additional material and cases to increase air space distance.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.124-130
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• 2023

Recently, fan out wafer level packaging, which enables high integration, miniaturization, and low cost, is being rapidly applied in the semiconductor industry. In particular, FOWLP is attracting attention in the mobile and Internet of Things fields, and is recognized as a core technology that will lead to technological advancements such as 5G, self-driving cars, and artificial intelligence in the future. However, as chip density and package size within the package increase, FOWLP warpage is emerging as a major problem. These problems have a direct impact on the reliability and electrical performance of semiconductor products, and in particular, cause defects such as vacuum leakage in the manufacturing process or lack of focus in the photolithography process, so technical demands for solving them are increasing. In this paper, warpage simulation according to the thickness of FOWLP material was performed using finite element analysis. The thickness range was based on the history of similar packages, and as a factor causing warpage, the curing temperature of the materials undergoing the curing process was applied and the difference in deformation due to the difference in thermal expansion coefficient between materials was used. At this time, the stacking order was reflected to reproduce warpage behavior similar to reality. After performing finite element analysis, the influence of each variable on causing warpage was defined, and based on this, it was confirmed that warpage was controlled as intended through design modifications.

• Journal of the Semiconductor & Display Technology
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• v.17 no.4
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• pp.86-90
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• 2018

Standards related to express the non-flatness of a wafer are reviewed and discussed, for example, bow, warp, and sori. Novel wafer warpage measurement method is proposed for 3D stacked IC application. The new way measures heat transfer from a heater to a wafer, which is a function of the contact area between these two surfaces and in turn, this contact area depends on the wafer warpage. Measurement options such as heating from room temperature and cooling from high temperature were experimentally examined. The heating method was found to be sensitive to environmental conditions. The cooling technique showed more robust and repeatable results and the further investigation for the optimal cooling condition is underway.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.1
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• pp.31-39
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• 2014

For mobile application, semiconductor packages are increasingly moving toward high density, miniaturization, lighter and multi-functions. Typical wafer level packages (WLP) is fan-in design, it can not meet high I/O requirement. The fan-out wafer level packages (FOWLPs) with reconfiguration technology have recently emerged as a new WLP technology. In FOWLP, warpage is one of the most critical issues since the thickness of FOWLP is thinner than traditional IC package and warpage of WLP is much larger than the die level package. Warpage affects the throughput and yield of the next manufacturing process as well as wafer handling and fabrication processability. In this study, we investigated the characteristics of warpage and main parameters which affect the warpage deformation of FOWLP using the finite element numerical simulation. In order to minimize the warpage, the characteristics of warpage for various epoxy mold compounds (EMCs) and carrier materials are investigated, and DOE optimization is also performed. In particular, warpage after EMC molding and after carrier detachment process were analyzed respectively. The simulation results indicate that the most influential factor on warpage is CTE of EMC after molding process. EMC material of low CTE and high Tg (glass transition temperature) will reduce the warpage. For carrier material, Alloy42 shows the lowest warpage. Therefore, considering the cost, oxidation and thermal conductivity, Alloy42 or SUS304 is recommend for a carrier material.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.41 no.6
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• pp.443-453
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• 2017

In flip chip technology, the conventional solder bump has been replaced with a copper (Cu) pillar bump owing to its higher input/output (I/O) density, finer pitch, and higher reliability. However, Cu pillar bump technology faces several issues, such as interconnect shorting and higher low-k stress due to stiffer Cu pillar structure when the conventional reflow process is used. Therefore, the thermal compression bonding (TCB) process has been adopted in the flip chip attachment process in order to reduce the package warpage and stress. In this study, we investigated the package warpage induced during the TCB process using a numerical analysis. The warpage of the TCB process was compared with that of the reflow process.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.22 no.1
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• pp.168-172
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• 2013

In 3D wafer-stacking technology, one of the major issues is wafer warpage. Especially, The important reason of warpage has been known due to CTE(Coefficient of Thermal Expansion) mismatch between materials. It was too hard to choose how to make the FE model for blanket structured wafer level 3D packaging, because the thickness of each layer in wafer level 3D packaging was too small (micro meter or nano meter scale) comparing with diameter of wafer (6 or 8 inches). In this study, the FE model using the shell element was selected and simulated by the ANSYS WorkBench to investigate effects of the CTE on the warpage. To verify the FE model, it was compared by experimental results.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.09a
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• pp.79-94
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• 2002

Root cause -Thermal expansion coefficient mismatch -Tape warpage -Initial die crack (die roughness) Guideline for failure prevention -Optimized tape/Substrate design for minimizing the warpage -Fine surface of die backside Root cause -Thermal expansion coefficient mismatch - Repetitive bending of a signal trace during TC cycle - Solder mask damage Guideline for failure prevention - Increase of trace width - Don't make signal trace passing the die edge - Proper material selection with thick substrate core Root cause -Thermal expansion coefficient mismatch -Creep deformation of solder joint(shear/normal) -Material degradation Guideline for failure Prevention -Increase of solder ball size -Proper selection of the PCB/Substrate thickness -Optimal design of the ball array -Solder mask opening type : NSMD -In some case, LGA type is better

• Composites Research
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• v.31 no.6
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• pp.404-411
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• 2018

As the autoclave process progresses in a given cure cycle, residual stress in the composite product is induced by cure shrinkage of the resin. As a result, It generates the thermal deformation such as spring-in and warpage, and the inaccuracy of the final product increases. It is important to predict thermal deformation in aerospace parts which require precise fabrication. The research has been done on predicting and grasping curing process of composite material. In this study, the cure mechanism of composite materials according to the process is predicted through finite element analysis, and the effect of cure shrinkage on thermal deformation generated by the process is analyzed.