[KSCI] Korea Science Citation Index Service

http://dx.doi.org/10.7735/ksmte.2013.22.1.168

Warpage Simulation by the CTE mismatch in Blanket Structured Wafer Level 3D packaging

Kim, Seong Keol (Department of Mechanical System Design Engineering, Seoul National University of Science and Technology)
Jang, Chong-Min (Graduate School of Mechanical Design & Automation Eng., Seoul National University of Science and Technology)
Hwang, Jung-Min (Department of Mechanical System Design Engineering, Seoul National University of Science and Technology)
Park, Man-Chul (Department of Mechanical System Design Engineering, Seoul National University of Science and Technology)

Publication Information

Journal of the Korean Society of Manufacturing Technology Engineers / v.22, no.1, 2013 , pp. 168-172 More about this Journal

Abstract

In 3D wafer-stacking technology, one of the major issues is wafer warpage. Especially, The important reason of warpage has been known due to CTE(Coefficient of Thermal Expansion) mismatch between materials. It was too hard to choose how to make the FE model for blanket structured wafer level 3D packaging, because the thickness of each layer in wafer level 3D packaging was too small (micro meter or nano meter scale) comparing with diameter of wafer (6 or 8 inches). In this study, the FE model using the shell element was selected and simulated by the ANSYS WorkBench to investigate effects of the CTE on the warpage. To verify the FE model, it was compared by experimental results.

Keywords

Solder joints; Warpage; FEM analysis; CTE; Wafer stacking;

Citations & Related Records

Reference

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