• Journal of the Korean Ceramic Society
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• v.36 no.1
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• pp.61-68
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• 1999

To analyze several defects and residual stress in sintering of layer structure materials, multiayer materials with TZP/SUS and ZT/SUS, and bilayer materials with porcelain/alumina and porcelain/Y-TZP were fabricated by sintering method. Multilayer materials prepared by pressureless sintering show the sintering defect such as warping, splitting, cracking originated from the difference of sintering shrinkage between each layer, which could be controlled by the adjustment of number and thickness in interlayer. In tape casting, a certain pressure given during sintering relaxed the sintering defects, specially warping. The residual stress in bilayer was examined with Vickers indentation method. A small tensile stress in porcelain/alumina and a large compressive stress in porcelain/Y-TZP were generated on the porcelain interface due to the thermal expansion mismatch, which affected the strength of bilayer materials. As a consequence, the sintering defects of multilayer materials and the residual stresses of bilayer materials were dominantly influenced on material design and starting material constants.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.11a
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• pp.39-47
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• 2002

Heat is always the root of stress acting upon the electronic package, regardless of the heat due to the device itself during operation or working under the adverse environment. Due to the significant mismatch in coefficient of thermal expansion (CTE) and the thermal conductivity (K) of the packaging components, on one hand intensive research has been conducted in order to enhance the device reliability by minimizing the mechanical stressing and deformation within the package. On the other hand the effectiveness of different thermal enhancements are pursued to dissipate the heat to avoid the overheating of the device. However, the interactions between the thermal-mechanical loading has not yet been address fully. in articular when the temperature gradient is considered within the package. To address the interactions between the thermal loading upon the mechanical stressing condition. coupled-field analysis is performed to account the interaction between the thermal and mechanical stress distribution. Furthermore, process induced defects are also incorporated into the analysis to determine the effects on thermal conducting path as well as the mechanical stress distribution. It is concluded that it feasible to consider the thermal gradient within the package accompanied with the mechanical analysis, and the subsequent effects of the inherent defects on the overall structural integrity of the package are discussed.

• Applied Microscopy
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• v.25 no.2
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• pp.73-79
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• 1995

The oxidation of silicon wafers is an essential step in the fabrication of semiconductor devices. It is known to induce degradation of electrical properties and lattice strain of Si substrate from thermal oxidation process due to charged interface and thermal expansion mismatch from thermally grown SiO, film. In this study, convergent beam electron diffraction technique is employed to directly measure the lattice strains in Si(100) and $4^{\circ}$ - off Si(100) substrates with thermally grown oxide layer at $1200^{\circ}C$ for three hours. The ratios of {773}-{973}/{773}-{953} Higher Order Laue Zone lines were used at [012] zone axis orientation. Lattice parameters of the Si substrate as a function of distance from the interface were determined from the computer simulation of diffraction patterns. Correction value for the accelerating voltage was 0.2kV for the kinematic simulation of the [012]. HOLZ patterns. The change in the lattice strain profile before and after removal of oxide films revealed the magnitudes of intrinsic strain and thermal strain components. It was shown that $4^{\circ}$ -off Si(100) had much lower intrinsic strain as surface steps provide effective sinks for the free Si atoms produced during thermal oxidation. Thermal strain in the Si substrate was in compression very close to the interface and high concentration of Si interstitials appeared to modify the thermal expansion coefficient of Si.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.11
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• pp.1672-1678
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• 1989

Major problems preventing the device-quality GaAs/Si heterostructure are the lattice mismatch of about 4% and difference in thermal expansion coefficient by a factor of 2.64 between Si and GaAs. Ge is a good candidate for the buffer layer because its lattice parameter and thermal expansion coefficient are almost the same as those of GaAs. As a first step toward developing heterostructure such as GaAs/Ge/Si entirely by a home-built PAE (plasma-assisted epitaxy), Ge films have been deposited on p-type Si (100)substrate by the plasma assisted evaporation of solid Ge source. The characteristics of these Ge/Si heterostructure were determined by X-ray diffraction, SEM and Auge electron spectroscope. PAE system has been successfully applied to quality-good Ge layer on Si substrate at relatively low temperature. Furthermore, this system can remove the native oxide(SiO2) on Si substrate with in-situ cleaning procedure. Ge layer grown on Si substrate by PAE at substrate temperature of 450\ulcorner in hydrogen partial pressure of 10mTorr was expected with a good buffer layer for GaAs/Ge/Si heterostructure.

• Journal of Applied Reliability
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• v.8 no.4
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• pp.155-166
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• 2008

PTH cracks are caused by the mismatch of coefficient of thermal expansion(CTE) between polymer and laminated materials, and are one of the main failure mechanisms of multi layer boards. In spite of its importance, it is usually hard to measure or detect them because of its small size and invisibility. To detect PTH cracks more effectively, this paper proposes a theoretical model that can estimate the resistance value from crack size of PTHs. Using four-point probe resistance measurement method, the resistance value of test coupons is measured. Through measured data, we verify the validity of the proposed theoretical model and set up criteria of failure.

• Steel and Composite Structures
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• v.17 no.2
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• pp.173-184
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• 2014

This study aimed to theoretical calculate the thermal residual stress in continuous SiC fiber reinforced titanium matrix composites. The analytical solution of residual stress field distribution was obtained by using coaxial cylinder model, and the numerical solution was obtained by using finite element model (FEM). Both of the above models were compared and the thermal residual stress was analyzed in the axial, hoop, radial direction. The results indicated that both the two models were feasible to theoretical calculate the thermal residual stress in continuous SiC fiber reinforced titanium matrix composites, because the deviations between the theoretical calculation results and the test results were less than 8%. In the titanium matrix composites, along with the increment of the SiC fiber volume fraction, the longitudinal property was improved, while the equivalent residual stress was not significantly changed, keeping the intensity around 600 MPa. There was a pronounced reduction of the radial residual stress in the titanium matrix composites when there was carbon coating on the surface of the SiC fiber, because carbon coating could effectively reduce the coefficient of thermal expansion mismatch between the fiber and the titanium matrix, meanwhile, the consumption of carbon coating could protect SiC fibers effectively, so as to ensure the high-performance of the composites. The support of design and optimization of composites was provided though theoretical calculation and analysis of residual stress.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.5
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• pp.434-439
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• 2008

Silver pastes as the outer electrodes have been prepared using Pb-free glass frits with different content of $Bi_2O_3$ and the effects of glass composition on the degradation behaviors of the Ag electrodes were investigated using the change of adhesion between Ag electrode and alumina substrate with thermal cycle stress. Low adhesion and high surface resistance were observed in Ag electrode using glass frit with a $Bi_2O_3$ content of 60 wt%, owing to the open microstructure formed at the firing temperature of $600^{\circ}C$. When the $Bi_2O_3$ was increased to 80 wt% in the glass frit, the Ag electrodes had a dense microstructure with high adhesion and a low surface resistance. Delamination of the Ag electrodes was a major failure mode under thermal cycle stress and this was attributed to residual stress due to the thermal expansion mismatch between the Ag electrode and the alumina substrate.

• Journal of the Microelectronics and Packaging Society
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• v.6 no.2
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• pp.13-21
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• 1999

Flip chip assembly directly on organic boards offers miniaturization of package size as well as reduction in interconnection distances resulting in a high performance and cost-competitive Packaging method. This paper describes the investigation of alternative low cost flip-chip mounting processes using electroless Ni/Au bump and anisotropic conductive adhesives/films as an interconnection material on organic boards such as FR-4. As bumps for flip chip, electroless Ni/Au plating was performed and characterized in mechanical and metallurgical point of view. Effect of annealing on Ni bump characteristics informed that the formation of crystalline nickel with $Ni_3$P precipitation above $300^{\circ}C$ causes an increase of hardness and an increase of the intrinsic stress resulting in a reliability limitation. As an interconnection material, modified ACFs composed of nickel conductive fillers for electrical conductor and non-conductive inorganic fillers for modification of film properties such as coefficient of thermal expansion(CTE) and tensile strength were formulated for improved electrical and mechanical properties of ACF interconnection. The thermal fatigue life of ACA/F flip chip on organic board limited by the thermal expansion mismatch between the chip and the board could be increased by a modified ACA/F. Three ACF materials with different CTE values were prepared and bonded between Si chip and FR-4 board for the thermal strain measurement using moire interferometry. The thermal strain of ACF interconnection layer induced by temperature excursion of $80^{\circ}C$ was decreased with decreasing CTEs of ACF materials.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.05a
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• pp.138-141
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• 2002

There are continuous efforts in the electronics industry to a reduced electronic package size. Reducing the size of electronic packages can be achieved by a variety of means, and for ball grid array(BGA) packages an effective method is to decrease the pitch between the individual balls. Chip scale package(CSP) and BGA are now one of the major package types. However, a reduced package size has the negative effect of reducing board-level reliability. The reliability concern is for the different thermal expansion rates of the two-substrate materials and how that coefficient CTE mismatch creates added stress to the BGA solder joint when thermal cycled. The point of thermal fatigue in a solder joint is an important factor of BGA packages and knowing at how many thermal cycles can be ran before failure in the solder BGA joint is a must for designing a reliable BGA package. Reliability of the package was one of main issues and underfill was required to improve board-level reliability. By filling between die and substrate, the underfill could enhance the reliability of the device. The effect of underfill on various thermomechanical reliability issues in $\mu$BGA packages is studied in this paper.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.22 no.1
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• pp.168-172
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• 2013

In 3D wafer-stacking technology, one of the major issues is wafer warpage. Especially, The important reason of warpage has been known due to CTE(Coefficient of Thermal Expansion) mismatch between materials. It was too hard to choose how to make the FE model for blanket structured wafer level 3D packaging, because the thickness of each layer in wafer level 3D packaging was too small (micro meter or nano meter scale) comparing with diameter of wafer (6 or 8 inches). In this study, the FE model using the shell element was selected and simulated by the ANSYS WorkBench to investigate effects of the CTE on the warpage. To verify the FE model, it was compared by experimental results.