• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1993.11a
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• pp.49-54
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• 1993

This paper discusses the reliability of solder joints of electronic devices on printed circuit board. Solder application is usually done by screen printing method for the bonding between outer leads of devices and thick film(Ag/Pd) pattern on Hybrid IC as wel1 as Cu lands on PCB. As result of thermal stresses generated at the solder joints due to the differences of thermal expansion coefficients between packge body and PCB, Micro cracking often occurs due to thermal fatigue failure at solder joints. The initiation and the propagate of solder joint crack depends on the environmental conditions, such as storage temperature and thermal cycling. The principal mechanisms of the cracking pheno- mana are the formation of kirkendal void caused by the differences in diffusion rate of materials, ant the thermal fatigue effect due to the differences of thermal expansion coefficient between package body and PCB. Finally, This paper experimentally shows a way to supress solder joints cracks by using low-${\alpha}$ PCB and the packages with thin lead frame, and investigates the phenomena of diffusion near the bonding interfaces.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.1092-1095
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• 2001

Steady state thermal analysis has been done by a finite element method in a diode of 12kV blocking voltage. The diode was fabricated by soldering ten pieces of 1200V diodes in series, capping a dummy wafer at the far end of diode series, and finally wire bonded for building anode and cathode terminal. In order to achieve high voltage and reliability, the edge of each diode was beveled and passivated by resin with a thickness of 25${\mu}$m. It was assumed that the generated heat which is mainly by the on-state voltage drop, 9V for 12kV diode, is dissipated by way of the conduction through diodes layers to bonding wire and of the convection at the surface of passivating resin. It was predicted by the thermal analysis that the temperature rise of a pn junction of the 12kV diode can reach at the range of 16∼34$^{\circ}C$ under the given boundary conditions. The thickness and thermal conductivity(0.3∼3W/m-K) of the passivating resin did little effect to lower thermal resistance of the diode. As the length of the bonding wire increased, which means the distance of heat conduction path became longer, the thermal resistance increased considerably. The thermal analysis results imply that the generated heat of the diode is dissipated mainly by the conduction through the route of diode-dummy wafer-bonding wire, which suggests to minimize the length of the wire for the lowest thermal resistance.

• Korean Journal of Materials Research
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• v.12 no.6
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• pp.508-512
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• 2002

$2000{\AA}-SiO_2/Si(100)$ and $560{\AA}-Si_3N_4/Si(100)$ wafers, which are 10 cm in diameter, were directly bonded using a rapid thermal annealing method. We fixed the anneal time of 30 second and varied the anneal temperatures from 600 to $1200^{\circ}C$. The bond strength of bonded wafer pairs at given anneal temperature were evaluated by a razor blade crack opening method and a four-point bonding method, respectively. The results clearly slow that the four-point bending method is more suitable for evaluating the small bond strength of 80~430 mJ/$\m^2$ compared to the razor blade crack opening method, which shows no anneal temperature dependence in small bond strength.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.10
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• pp.859-864
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• 2003

We prepared SOI(silicon-on-insulator) wafer pairs of Si II SiO$_2$/Si$_3$N$_4$ II Si using wafer direct bonding with an electric furnace annealing(EFA), a fast linear annealing(FLA), and a rapid thermal annealing(RTA), respectively, by varying the annealing temperatures at a given annealing process. We measured the bonding area and the bonding strength with processes. EFA and FLA showed almost identical bonding area and theoretical bonding strength at the elevated temperature. RTA was not bonded at all due to warpage, We report that FLA process was superior to other annealing processes in aspects of surface temperature, annealing time, and bonding strength.

• Korean Journal of Materials Research
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• v.16 no.2
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• pp.99-105
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• 2006

This paper reports an improved bonding method using the IPA (isopropyl alcohol) assisted low-temperature bonding process for the PMMA (polymethylmethacrylate) micro CE (capillary electrophoresis) chip. There is a problem about channel deformations during the conventional processes such as thermal bonding and solvent bonding methods. The bonding test using an IPA showed good results without channel deformations over 4 inch PMMA wafer at $60^{\circ}C$ and 1.3 bar for 10 minutes. The mechanism of IPA bonding was attributed to the formation of a small amount of vaporized acetone made from the oxidized IPA which allows to solvent bonding. To verify the usefulness of the IPA assisted low-temperature bonding process, the PMMA micro CE chip which had a $45{\mu}m$ channel height was fabricated by hot embossing process. A functional test of the fabricated CE chip was demonstrated by the separation of fluorescein and dichlorofluorescein. Any leakage of liquids was not observed during the test and the electropherogram result was successfully achieved. An IPA assisted low-temperature bonding process could be an easy and effective way to fabricate the PMMA micro CE chip and would help to increase the yield.

• Korean Journal of Materials Research
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• v.17 no.3
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• pp.152-159
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• 2007

When the electronics are tested with thermal shock for Pb-free solder joint reliability, there are temperature conditions with use environment but number of cycles for test don't clearly exist. To obtain the long term reliability data, electronic companies have spent the cost and times. Therefore this studies show the test method and number of thermal shock cycles for evaluating the solder joint reliability of electronic components and also research bonding strength variation with formation and growth of intermetallic compounds (IMC). SMD (surface mount device) 3216 chip resistor and 44 pin QFP (quad flat package) was utilized for experiments and each components were soldered with Sn-40Pb and Sn-3.0 Ag-0.5 Cu solder on the FR-4 PCB(printed circuit board) using by reflow soldering process. To reliability evaluation, thermal shock test was conducted between $-40^{\circ}C\;and\;+125^{\circ}C$ for 2,000 cycles, 10 minute dwell time, respectively. Also we analyzed the IMCs of solder joint using by SEM and EDX. To compare with bonding strength, resistor and QFP were tested shear strength and $45^{\circ}$ lead pull strength, respectively. From these results, optimized number of cycles was proposed with variation of bonding strength under thermal shock.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.31 no.1 s.256
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• pp.113-120
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• 2007

Design optimization of layered plates bonding process is conducted by considering uncertainties in a manufacturing process, in order to reduce the crack failure arising due to the residual stress at the surface of the adherent which is caused by different thermal expansion coefficients. Robust optimization is peformed to minimize the mean as well as its variance of the residual stress, while constraining the distortion as well as the instantaneous maximum stress under the allowable reliability limits. In this optimization, the dimension reduction (DR) method is employed to quantify the reliability such as mean and variance of the layered plate bonding. It is expected that the DR method benefits the optimization from the perspectives of efficiency, accuracy, and simplicity. The obtained robust optimal solution is verified by the Monte Carlo simulation.

• Proceedings of the Optical Society of Korea Conference
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• 2002.07a
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• pp.254-255
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• 2002

Optical elements such as small glass lenses or optical fibers can be permanently bonded to substrates using Al inter-layer by applying Pressure and heating. As an example aspherical lens was bonded on a silicon V-groove. The bonding has high shear strength and good thermal cycling stability.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.23 no.4
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• pp.355-360
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• 2014

Recently, the use of LED is increasing. This paper presents the new package process of thermal compression bonding using metal layered LED chip for the high power LED device. Effective thermal dissipation, which is required in the high power LED device, is achieved by eutectic/flip chip bonding method using metal bond layer on a LED chip. In this study, the process condition for the LED eutectic die bonder system is proposed by using the analysis program, and some experimental results are compared with those obtained using a DST (Die Shear Tester) to illustrate the reliability of the proposed process condition. The cause of bonding failures in the proposed process is also investigated experimentally.

• Proceedings of the KIEE Conference
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• 1998.07g
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• pp.2501-2503
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• 1998

In this paper, the silicon-nitride membrane structure for IR sensor was fabricated through the etching and the direct bonding. The PTO layer as a IR detection layer was deposited on the membrane and its characteristics were measured. The attack of PTO layer during the etching of silicon wafer as well as the thermal isolation of the IR detection layer can be solved through the method of bonding/etching of silicon wafer. Because the PTO layer of c-axial orientation raised thermal polarization without polling, the more integration capability can be achieved. The surface roughness of the membrane was measured by AFM, the micro voids and the non-contacted area were inspected by IR detector, and the bonding interface was observed by SEM. The polarization characteristics and the dielectric characteristics of the PTO layer were measured, too.