• Journal of information and communication convergence engineering
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• v.12 no.3
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• pp.186-192
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• 2014

Monolithic three-dimensional integrated chips (3D ICs) are an emerging technology that offers an integration density that is some orders of magnitude higher than the conventional through-silicon-via (TSV)-based 3D ICs. This is due to a sequential integration process that enables extremely small monolithic inter-tier vias (MIVs). For a monolithic 3D memory, we first explore the static random-access memory (SRAM) design. Next, for digital logic, we explore several design styles. The first is transistor-level, which is a design style unique to monolithic 3D ICs that are enabled by the ultra-high-density of MIVs. We also explore gate-level and block-level design styles, which are available for TSV-based 3D ICs. For each of these design styles, we present techniques to obtain the graphic database system (GDS) layouts, and perform a signoff-quality performance and power analysis. We also discuss various challenges facing monolithic 3D ICs, such as achieving 50% footprint reduction over two-dimensional (2D) ICs, routing congestion, power delivery network design, and thermal issues. Finally, we present design techniques to overcome these challenges.

• Journal of Sensor Science and Technology
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• v.22 no.1
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• pp.89-94
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• 2013

In this paper, we developed a beam of MEMS probe card using a BeCu sheet. Silicon wafer thickness of $400{\mu}m$ was fabricated by using deep reactive ion etching (RIE) process. After forming through silicon via (TSV), the silicon wafer was bonded with BeCu sheet by soldering process. We made BeCu beam stress-free owing to removing internal stress by using joule heating. BeCu beam was fused by using joule heating caused by high current. The fabricated BeCu beam measured length of 1.75 mm and width of 0.44 mm, and thickness of $15{\mu}m$. We measured fusing current as a function of the cutting planes. Maximum current was 5.98 A at cutting plane of $150{\mu}m^2$. The proposed low-cost and simple fabrication process is applicable for producing MEMS probe beam.

• Journal of the Optical Society of Korea
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• v.17 no.4
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• pp.317-322
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• 2013

We have proposed and demonstrated a low numerical aperture technique to measure the depth of through silicon vias (TSVs) using white-light scanning interferometry. The high aspect ratio hole like TSV's was considered to be impossible to measure using conventional optical methods due to low visibility at the bottom of the hole. We assumed that the limitation of the measurement was caused by reflection attenuation in TSVs. A novel interference theory which takes the structural reflection attenuation into consideration was proposed and simulated. As a result, we figured out that the low visibility in the interference signal was caused by the unbalanced light intensity between the object and the reference mirror. Unbalanced light can be balanced using an aperture at the illumination optics. As a result of simulation and experiment, we figured out that the interference signal can be enhanced using the proposed technique. With the proposed optics, the depth of TSVs having an aspect ratio of 11.2 was measured in 5 seconds. The proposed method is expected to be an alternative method for 3-D inspection of TSVs.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2009.05a
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• pp.247-247
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• 2009

3차원 반도체 패키징에서 관통전극 Through Silicon Via (TSV)를 형성하기 위하여 이온과 래디컬의 활성도 조절이 가능한 pulsating inductively coupled plasma (ICP) 식각을 수행하였다. 본 식각공정에서는 펄스주파수 ($50{\sim}500Hz$)와 듀티 싸이클 ($20{\sim}99%$)을 조절하여, 플라즈마 내 이온과 래디컬들의 활성도 변화를 발생시켰다. 플라즈마 공정변수에 따라 식각형태가 달라짐을 S.E.M을 이용하여 확인했으며, 이온(SFx+, O+)과 래디컬 ($SF^*$, $F^*$, $O^*$)의 농도 및 활성도 변화를 측정하기 위하여 광학적 기술인 optical emissin spectroscopy와 전기적 특성 측정 기술인 Langmuir probe 시스템을 직접 제작 설치하여 펄스플라즈마를 진단하였다.

• ETRI Journal
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• v.36 no.4
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• pp.635-642
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• 2014

Three-dimensional integrated circuits (3D ICs) implement heterogeneous systems in the same platform by stacking several planar chips vertically with through-silicon via (TSV) technology. 3D ICs have some advantages, including shorter interconnect lengths, higher integration density, and improved performance. Thermal-aware design would enhance the reliability and performance of the interconnects and devices. In this paper, we propose thermal-aware floorplanning with min-cut die partitioning for 3D ICs. The proposed min-cut die partition methodology minimizes the number of connections between partitions based on the min-cut theorem and minimizes the number of TSVs by considering a complementary set from the set of connections between two partitions when assigning the partitions to dies. Also, thermal-aware floorplanning methodology ensures a more even power distribution in the dies and reduces the peak temperature of the chip. The simulation results show that the proposed methodologies reduced the number of TSVs and the peak temperature effectively while also reducing the run-time.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.2
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• pp.23-34
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• 2013

Over the past several decades in the microelectronics industry, devices have gotten smaller, thinner, and lighter, without any accompanying degradation in quality, performance, and reliability. One permanent and deniable trend in packaging as well as wafer fabrication industry is system integration. The proliferating options for system integration, recently, are driving change across the overall semiconductor industry, requiring more investment in developing, ramping and supporting new die-, wafer- and board-level solution. The trend toward 3D system integration and miniaturization in a small form factor has accelerated even more with the introduction of smartphones and tablets. In this paper, the key issues and state of the art for system integration in the packaging process are introduced, especially, focusing on ease transition to next generation packaging technologies like through silicon via (TSV), 3D wafer-level fan-out (WLFO), and chip-on-chip interconnection. In addition, effective solutions like fine pitch copper pillar and MEMS packaing of both advanced and legacy products are described with several examples.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.137-137
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• 2010

Copper electroplating is a very popular and important technology for depositing high-quality conductor interconnections, especially in through silicon via (TSV). As this advanced packaging technique developing, a mass of copper and chemical solution are used, so attention to these chemical materials into the utilization and costs can not be ignored. An economical and practical real-time chemical solution monitoring has not been achieved yet. Either Red-green-blue (RGB) or optical emission spectroscopy (OES) color sensor can successfully monitor the color condition of solution during the process. The reaction rate, uniformity and quality can map onto the color changing. Hidden Semi Markov model (HSMM) can establish mapping from the color change to upper indicators, and artificial neural network (ANN) can be integrated to comprehensively determine its targets, whether the solution inside the container can continue to use.

• Journal of the Korean Society for Nondestructive Testing
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• v.35 no.3
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• pp.200-205
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• 2015

An ultra-precise infrared microscope consisting of a high-resolution infrared objective lens and infrared sensors is utilized successfully to obtain location information on the plane and depth of local heat sources causing defects in a semiconductor device. In this study, multi-layer semiconductor chips are analyzed for the positional information of heat sources by using a lock-in infrared microscope. Optimal conditions such as focal position, integration time, current and lock-in frequency for measuring the accurate depth of the heat sources are studied by lock-in thermography. The location indicated by the results of the depth estimate, according to the change in distance between the infrared objective lens and the specimen is analyzed under these optimal conditions.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.4
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• pp.9-17
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• 2017

In these days, MEMS (micro-electro-mechanical system) devices become the crucial sensor components in mobile devices, automobiles and several electronic consumer products. For MEMS devices, the packaging determines the performance, reliability, long-term stability and the total cost of the MEMS devices. Therefore, the packaging technology becomes a key issue for successful commercialization of MEMS devices. As the IoT and wearable devices are emerged as a future technology, the importance of the MEMS sensor keeps increasing. However, MEMS devices should meet several requirements such as ultra-miniaturization, low-power, low-cost as well as high performances and reliability. To meet those requirements, several innovative technologies are under development such as integration of MEMS and IC chip, TSV(through-silicon-via) technology and CMOS compatible MEMS fabrication. It is clear that MEMS packaging will be key technology in future MEMS. In this paper, we reviewed the recent development trends of the MEMS packaging. In particular, we discussed and reviewed the recent technology trends of the MEMS bonding technology, such as low temperature bonding, eutectic bonding and thermo-compression bonding.

• Journal of the Korean Society for Precision Engineering
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• v.31 no.10
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• pp.865-871
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• 2014

Paradigm shift to 3-D chip stacking in electronic packaging has induced a lot of integration challenges due to the reduction in wafer thickness and pitch size. This study presents a hybrid bonding technology by self-alignment effect in order to improve the flip chip bonding accuracy with ultra-thin wafer. Optimization of Cu pillar bump formation and evaluation of various factors on self-alignment effect was performed. As a result, highly-improved bonding accuracy of thin wafer with a $50{\mu}m$ of thickness was achieved without solder bridging or bump misalignment by applying reflow process after thermo-compression bonding process. Reflow process caused the inherently-misaligned micro-bump to be aligned due to the interface tension between Si die and solder bump. Control of solder bump volume with respect to the chip dimension was the critical factor for self-alignment effect. This study indicated that bump design for 3D packaging could be tuned for the improvement of micro-bonding quality.