• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2016.11a
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• pp.128-128
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• 2016

Cu 배선폭 미세화 기술은 반도체 디바이스의 성능 향상을 위한 핵심 기술이다. 현재 배선 기술은 lithography, deposition, planarization등 종합적인 공정 기술의 발전에 따라 10x nm scale까지 감소하였다. 하지만 지속적인 feature size 감소를 위하여 요구되는 높은 공정 기술 및 비용과 배선폭 미세화로 인한 재료의 물리적 한계로 인하여 배선폭 미세화를 통한 성능의 향상에는 한계가 있다. 배선폭 미세화를 통한 2차원적인 집적도 향상과는 별개로 chip들의 3차원 적층을 통하여 반도체 디바이스의 성능 향상이 가능하다. 칩들의 3차원 적층을 위해서는 별도의 3차원 배선 기술이 요구되는데, TSV(through-Si-via)방식은 Si기판을 관통하는 via를 통하여 chip간의 전기신호 교환이 최단거리에서 이루어지는 가장 진보된 형태의 3차원 배선 기술이다. Si 기판에 $50{\mu}m$이상 깊이의 via 및 seed layer를 형성 한 후 습식전해증착법을 이용하여 Cu 배선이 이루어지는데, via 내부 Cu ion 공급 한계로 인하여 일반적인 공정으로는 void와 같은 defect가 형성되어 배선 신뢰성에 문제를 발생시킨다. 이를 해결하기 위해 각종 유기 첨가제가 사용되는데, suppressor를 사용하여 Si 기판 상층부와 via 측면벽의 Cu 증착을 억제하고, accelerator를 사용하여 via 바닥면의 Cu 성장속도를 증가시켜 bottom-up TSV filling을 유도하는 방식이 일반적이다. 이론적으로, Bottom-up TSV filling은 sample 전체에서 Cu 성장을 억제하는 suppressor가 via bottom의 강한 potential로 인하여 국부적 탈착되고 via bottom에서만 Cu가 증착되어 되어 이루어지므로, accelerator가 없이도 void-free TSV filling이 가능하다. Accelerator가 Suppressor를 치환하여 오히려 bottom-up TSV filling을 방해한다는 보고도 있었다. 본 연구에서는 유기 첨가제의 치환으로 인한 TSV filling performance 저하를 방지하고, 유기 첨가제 조성을 단순화하여 용액 관리가 용이하도록 하기 위하여 suppressor만을 이용한 TSV filling 연구를 진행하였다. 먼저, suppressor의 흡착, 탈착 특성을 이해하기 위한 연구가 진행되었고, 이를 바탕으로 suppressor만을 이용한 bottom-up Cu TSV filling이 진행되었다. 최종적으로 $60{\mu}m$ 깊이의 TSV를 1000초 내에 void-free filling하였다.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.1
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• pp.69-73
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• 2010

Finite-element analyses were conducted to investigate the thermal stress in 3-dimensional stacked wafers package containing through-silicon-via (TSV), which is being widely used for 3-Dimensional integration. With finite element method (FEM), thermal stress was analyzed with the variation of TSV diameter, bonding diameter, pitch and TSV height. It was revealed that the maximum von Mises stresses occurred at the edge of top interface between Cu TSV and Si and the Si to Si bonding site. As TSV diameter increased, the von Mises stress at the edge of TSV increased. As bonding diameter increased, the von Mises stress at Si to Si bonding site increased. As pitch increased, the von Mises stress at Si to Si bonding site increased. The TSV height did not affect the von Mises stress. Therefore, it is expected that smaller Cu TSV diameter and pitch will ensure mechanical reliability because of the smaller chance of plastic deformation and crack initiation.

• Journal of Welding and Joining
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• v.32 no.3
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• pp.11-18
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• 2014

TSV(through silicon via) filling technology is making a hole in Si wafer and electrically connecting technique between front and back of Si die by filling with conductive metal. This technology allows that a three-dimensionally connected Si die can make without a large number of wire-bonding. These TSV technologies require various engineering skills such as forming a via hole, forming a functional thin film, filling a conductive metal, polishing a wafer, chip stacking and TSV reliability analysis. This paper addresses the TSV filling using Cu electrodeposition. The impact of plating conditions with additives and current density on electrodeposition will be considered. There are additives such as accelerator, inhibitor, leveler, etc. suitably controlling the amount of the additive is important. Also, in order to fill conductive material in whole TSV hole, current wave forms such as PR(pulse reverse), PPR(periodic pulse reverse) are used. This study about semiconductor packaging will be able to contribute to the commercialization of 3D TSV technology.

• Journal of the Microelectronics and Packaging Society
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• v.29 no.4
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• pp.1-8
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• 2022

High-density packaging technologies, including Through-Si-Via (TSV) technologies, are considered important in many fields such as IoT (internet of things), 6G/5G (generation) communication, and high-performance computing (HPC). Achieving high integration in two dimensional packaging has confronted with physical limitations, and hence various studies have been performed for the three-dimensional (3D) packaging technologies. In this review, we described about the causes and effects of scallop formation in TSV, the scallop-free etching technique for creating smooth sidewalls, Cu pillar and Cu-SiO₂ hybrid bonding in TSV. These technologies are expected to have effects on the formation of high-quality TSVs and the development of 3D packaging technologies.

• Journal of Welding and Joining
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• v.32 no.3
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• pp.68-73
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• 2014

Among through silicon via (TSV) technologies, for replacing Cu filling method, the method of molten solder filling has been proposed to reduce filling cost and filling time. However, because Sn alloy which has a high coefficient of thermal expansion (CTE) than Cu, CTE mismatch between Si and molten solder induced higher thermal stress than Cu filling method. This thermal stress can deteriorate reliability of TSV by forming defects like void, crack and so on. Therefore, we fabricated SiC composite filling material which had a low CTE for reducing thermal stress in TSV. To add SiC nano particles to molten solder, ball-typed SiC clusters, which were formed with Sn powders and SiC nano particles by ball mill process, put into molten Sn and then, nano particle-dispersed SiC composite filling material was produced. In the case of 1 wt.% of SiC particle, the CTE showed a lowest value which was a $14.8ppm/^{\circ}C$ and this value was lower than CTE of Cu. Up to 1 wt.% of SiC particle, Young's modulus increased as wt.% of SiC particle increased. And also, we observed cross-sectioned TSV which was filled with 1 wt.% of SiC particle and we confirmed a possibility of SiC composite material as a TSV filling material.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.3
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• pp.79-84
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• 2010

Formation of TSV (Through-Si-Via) with an Au seed layer and Cu filling to the via, simplification of bumping process for three dimensional stacking of Si dice were investigated. In order to produce the via holes, the Si wafer was etched by a DRIE (Deep Reactive Ion Etching) process using $SF_6$ and $C_4F_8$ plasmas alternately. The vias were 40 ${\mu}m$ in diameter, 80 ${\mu}m$ in depth, and were produced by etching for 1.92 ks. On the via side wall, a dielectric layer of $SiO_2$ was formed by thermal oxidation, and an adhesion layer of Ti, and a seed layer of Au were applied by sputtering. Electroplating with pulsed DC was applied to fill the via holes with Cu. The plating condition was at a forward pulse current density of 1000 mA/$dm^2$ for 5 s and a reverse pulse current density of 190 mA/$dm^2$ for 25 s. By using these parameters, sound Cu filling was obtained in the vias with a total plating time of 57.6 ks. Sn bumping was performed on the Cu plugs without lithography process. The bumps were produced on the Si die successfully by the simplified process without serious defect.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.2
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• pp.65-74
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• 2013

The through-silicon via (TSV) technology is essential for 3-dimensional integrated packaging. TSV technology, however, is still facing several reliability issues including interfacial delamination, crack generation and Cu protrusion. These reliability issues are attributed to themo-mechanical stress mainly caused by a large CTE mismatch between Cu via and surrounding Si. In this study, the thermo-mechanical reliability of copper TSV technology is investigated using numerical analysis. Finite element analysis (FEA) was conducted to analyze three dimensional distribution of the thermal stress and strain near the TSV and the silicon wafer. Several parametric studies were conducted, including the effect of via diameter, via-to-via spacing, and via density on TSV stress. In addition, effects of annealing temperature and via size on Cu protrusion were analyzed. To improve the reliability of the Cu TSV, small diameter via and less via density with proper via-to-via spacing were desirable. To reduce Cu protrusion, smaller via and lower fabrication temperature were recommended. These simulation results will help to understand the thermo-mechanical reliability issues, and provide the design guideline of TSV structure.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2008.11a
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• pp.21-22
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• 2008

$SF_6/O_2$ 플라즈마 에칭을 통한 반도체 칩의 3차원 집적에 응용되는 through-silicon-via (TSV) 구조형성 연구를 수행하였다. Si via 형상은 $SF_6$, $O_2$의 가스 비율과 에칭이 되는 Silicon 기판의 온도에 의존함을 알수 있었다. 또한 Si via 형상에서 최소의 언더컷 (undercut) 과 측벽에칭 (local bowing) 은 black Si이 나타나는 공정조건에서 나타남을 확인하였다. 더 나아가 저온을 이용한 via 형성시 via 측벽에 형성되는 passivation layer와 mask의 성질이 저온으로 인해 high-aspect-ratio를 갖는 via를 형성할 수 있음을 알 수 있었다.

• Korean Journal of Metals and Materials
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• v.49 no.5
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• pp.388-394
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• 2011

High speed copper filling into TSV (through-silicon-via) for three dimensional stacking of Si chips was investigated. For this study, a tapered via was prepared on a Si wafer by the DRIE (deep reactive ion etching) process. The via had a diameter of 37${\mu}m$ at the via opening, and 32${\mu}m$ at the via bottom, respectively and a depth of 70${\mu}m$. $SiO_2$, Ti, and Au layers were coated as functional layers on the via wall. In order to increase the filling ratio of Cu into the via, a PPR (periodic pulse reverse) wave current was applied to the Si chip during electroplating, and a PR (pulse reverse) wave current was applied for comparison. After Cu filling, the cross sections of the vias was observed by FE-SEM (field emission scanning electron microscopy). The experimental results show that the tapered via was filled to 100% at -5.85 mA/$cm^2$ for 60 min of plating by PPR wave current. The filling ratio into the tapered via by the PPR current was 2.5 times higher than that of a straight via by PR current. The tapered via by the PPR electroplating process was confirmed to be effective to fill the TSV in a short time.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.4
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• pp.49-53
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• 2011

High-speed Cu filling into a through-silicon-via (TSV) and simplification of bumping process by electroplating for three dimensional stacking of Si dice were investigated. The TSV was prepared on a Si wafer by deep reactive ion etching, and $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. In order to increase the filling rate of Cu into the via, a periodic-pulse-reverse wave current was applied to the Si chip during electroplating. In the bumping process, Sn-3.5Ag bumping was performed on the Cu plugs without lithography process. After electroplating, the cross sections of the vias and appearance of the bumps were observed by using a field emission scanning electron microscope. As a result, voids in the Cu-plugs were produced by via blocking around via opening and at the middle of the via when the vias were plated for 60 min at -9.66 $mA/cm^2$ and -7.71 $mA/cm^2$, respectively. The Cu plug with a void or a defect led to the production of imperfect Sn-Ag bump which was formed on the Cu-plug.