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Scallop-free TSV, Copper Pillar and Hybrid Bonding for 3D Packaging

3D 패키징을 위한 Scallop-free TSV와 Cu Pillar 및 하이브리드 본딩

  • Jang, Ye Jin (Dept. of Materials Science and Engineering, University of Seoul) ;
  • Jung, Jae Pil (Dept. of Materials Science and Engineering, University of Seoul)
  • 장예진 (서울시립대학교 신소재공학과) ;
  • 정재필 (서울시립대학교 신소재공학과)
  • Received : 2022.12.16
  • Accepted : 2022.12.28
  • Published : 2022.12.30

Abstract

High-density packaging technologies, including Through-Si-Via (TSV) technologies, are considered important in many fields such as IoT (internet of things), 6G/5G (generation) communication, and high-performance computing (HPC). Achieving high integration in two dimensional packaging has confronted with physical limitations, and hence various studies have been performed for the three-dimensional (3D) packaging technologies. In this review, we described about the causes and effects of scallop formation in TSV, the scallop-free etching technique for creating smooth sidewalls, Cu pillar and Cu-SiO2 hybrid bonding in TSV. These technologies are expected to have effects on the formation of high-quality TSVs and the development of 3D packaging technologies.

TSV 기술을 포함한 고밀도, 고집적 패키징 기술은 IoT, 6G/5G 통신, HPC (high-performance computing)등 여러 분야에서 중요한 기술로 여겨지고 있다. 2차원에서 고집적화를 달성하는 것은 물리적 한계에 도달하게 되었으며, 따라서 3D 패키징 기술을 위하여 다양한 연구들이 진행되고 있다. 본 고에서는 scallop의 형성 원인과 영향, 매끈한 측벽을 만들기 위한 scallop-free 에칭 기술, TSV 표면의 Cu bonding에 대해서 자세히 조사하였다. 이러한 기술들은 고품질 TSV 형성 및 3D 패키징 기술에 영향을 줄 것으로 예상한다.

Keywords

Acknowledgement

본 연구는 산업통상자원부 및 산업기술평가관리원(KEIT)의 소재부품기술개발사업 연구비 지원에 의해 수행되었습니다. ('20010580', 미니-LED 미세전극 접합을 위한 도전성 나노소재 기술 개발)

References

  1. Y. Jung, D. Ryu, M. Gim, C. Kim, Y. Song, J. Kim, J. Yoon, and C. Lee, "Development of next generation flip chip interconnection technology using homogenized laser-assisted bonding", IEEE 66th Electronic Components and Technology Conference (ECTC), 88-94 (2016).
  2. K. H. Beak, D. P. Kim, K. S. Park, J. Y. Kang, K. J. Lee, and L. M. Do, "DRIE Technology for TSV Fabrication", J. Korean Soc. Precis. Eng., 26(12), 32-40 (2009).
  3. N. Ranganathan, D. Y. Lee, L. Youhe, G. Q. Lo, K. Prasad, and K. L. Pey, "Influence of Bosch etch process on electrical isolation of TSV structures", IEEE Trans. Compon. Packag. Manuf. Technol., 1(10), 1497-1507 (2011). https://doi.org/10.1109/TCPMT.2011.2160395
  4. J. W. Choi, O. L. Guan, M. Yingjun, H. B. M. Yusoff, X. Jielin, C. C. Lan, W. L. Loh, B. L. Lau, L. L. H. Hong, L. G. Kian, R. Murthy, and E. T. S. Kiat, "TSV Cu filling failure modes and mechanisms causing the failures", IEEE Trans. Compon. Packag. Manuf. Technol., 4(4), 581-587 (2014). https://doi.org/10.1109/TCPMT.2014.2298031
  5. T. Nakamura, H. Kitada, Y. Mizushima, N. Maeda, K. Fujimoto, and T. Ohba, "Comparative study of side-wall roughness effects on leakage currents in through-silicon via interconnects", Proc. IEEE Int. 3D Syst. Integr. Conf., 1-4 (2012).
  6. H. Liu, Q. Zeng, Y. Guan, R. Fang, X. Sun, F. Su, J. Chen, M. Miao, and Y. Jin, "Thermal-mechanical reliability assessment of TSV structure for 3D IC integration", In 2016 IEEE 18th Electronics Packaging Technology Conference (EPTC), 758-764 (2016).
  7. Y. C. Hsin, C. C. Chen, J. H. Lau, P. J. Tzeng, S. H. Shen, Y. F. Hsu, S. C. Chen, C. Y. Wn, J. C. Chen, T. K. Ku, and M. J. Kao, "Effects of etch rate on scallop of through-silicon vias (TSVs) in 200mm and 300mm wafers", In 2011 IEEE 61st Electronic Components and Technology Conference (ECTC), 1130-1135 (2011).
  8. D. H. Jung, S. Kumar, and J. P. Jung, "Cu Electroplating and Low Alpha Solder Bumping on TSV for 3-D Packaging", J. Microelectron. Electron. Packag., 22(4), 7-14 (2015). https://doi.org/10.6117/kmeps.2015.22.4.007
  9. T. Tillocher, R. Dussart, L. J. Overzet, X. Mellhaoui, P. Lefaucheux, M. Boufnichel, and P. Ranson, "Two cryogenic processes involving SF6, O2, and SiF4 for silicon deep etching", J. Electrochem. Soc., 155(3), 187 (2008).
  10. Y. Wu, D. L. Olynick, A. Goodyear, C. Peroz, S. Dhuey, X. Liang, and S. Cabrini, "Cryogenic etching of nano-scale silicon trenches with resist masks", Microelectron. Eng., 88(8), 2785-2789 (2011). https://doi.org/10.1016/j.mee.2010.11.055
  11. K. A. Addae-Mensah, S. Retterer, S. R. Opalenik, D. Thomas, N. V. Lavrik, and J. P. Wikswo, "Cryogenic etching of silicon: an alternative method for fabrication of vertical microcantilever master molds", J. Microelectromech. Syst., 19(1), 64-74 (2009). https://doi.org/10.1109/JMEMS.2009.2037440
  12. S. L. Burkett, M. B. Jordan, R. P. Schmitt, L. A. Menk, and A. E. Hollowell, "Tutorial on forming through-silicon vias", J. Vac. Sci. Technol. A J VAC SCI TECHNOL A, 38(3), 031202 (2020). https://doi.org/10.1116/6.0000026
  13. H. V. Jansen, M. J. de Boer, S. Unnikrishnan, M. C. Louwerse, and M. C. Elwenspoek, "Black silicon method X: a review on high speed and selective plasma etching of silicon with profile control: an in-depth comparison between Bosch and cryostat DRIE processes as a roadmap to next generation equipment", J. Micromech. Microeng., 19(3), 033001 (2009). https://doi.org/10.1088/0960-1317/19/3/033001
  14. Y. Morikawa, "Plasma Etching Technology for Advanced Packaging to Lead Moore's Law(in Japanese)", J. Jpn. Inst. Electron. Packag., 25(1), 47-53 (2022). https://doi.org/10.5104/jiep.25.47
  15. R. F. Figueroa, S. Spiesshoefer, S. L. Burkett, and L. Schaper, "Control of sidewall slope in silicon vias using SF 6/O 2 plasma etching in a conventional reactive ion etching tool", J. Vac. Sci. Technol. B., 23(5), 2226-2231 (2005). https://doi.org/10.1116/1.2041654
  16. T. Maruyama, T. Narukage, R. Onuki, and N. Fujiwara, "High-aspect-ratio deep Si etching in SF 6/O 2 plasma. II. Mechanism of lateral etching in high-aspect-ratio features", J. Vac. Sci. Technol. B., 28(4), 862-868 (2010). https://doi.org/10.1116/1.3466884
  17. V. T. H. Nguyen, E. Shkondin, F. Jensen, J. Hubner, P. Leussink, and H. Jansen, "Ultrahigh aspect ratio etching of silicon in SF6-O2 plasma: The clear-oxidize-remove-etch (CORE) sequence and chromium mask", J. Vac. Sci. Technol. A, 38(5), 053002 (2020). https://doi.org/10.1116/6.0000357
  18. K. Hanaoka and K. Takahashi, "Vertical silicon etching by using an automatically and fast-controlled frequency tunable rf plasma source", AIP Adv., 11(2), 025013 (2021). https://doi.org/10.1063/5.0038596
  19. K. Hanaoka, K. Takahashi, and A. Ando, "Reproducibility of a plasma production in a fast-and automatically-controlled radio frequency plasma source", IEEE Trans. Plasma Sci., 48(6), 2138-2142 (2020). https://doi.org/10.1109/tps.2020.2987554
  20. Y. Morikawa, T. Murayama, T. Sakuishi, M. Yoshii, and K. Suu, "A novel scallop free TSV etching method in magnetic neutral loop discharge plasma", In 2012 IEEE 62nd Electronic Components and Technology Conference, 794-795 (2012).
  21. G. H. Wong, K. J. Chui, G. K. Lau, L. L. Woon, and L. HongYu, "Through silicon via (TSV) scallop smoothening technique," In 2014 IEEE 16th Electronics Packaging Technology Conference (EPTC), 676-678 (2014).
  22. G. Hwang, J. H. Miao, and B. C. Rao, "Development of Metallization Process for Fine Pitch TSV", In 2021 IEEE 23rd Electronics Packaging Technology Conference (EPTC), 633- 636 (2021).
  23. I. H. Jeong, A. Eslami Majd, J. P. Jung, and N. N. Ekere, "Electrical and mechanical analysis of different TSV geometries", Metals, 10(4), 467 (2020). https://doi.org/10.3390/met10040467
  24. W. S. Tsai, C. Y. Huang, C. K. Chung, K. H. Yu, and C. F. Lin, "Generational changes of flip chip interconnection technology", In 2017 12th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 306-310 (2017).
  25. Tung. F, "Pillar connections for semiconductor chips and method of manufacture", US Patent, No. 6,578,754., (2003)
  26. M. Gerber, C. Beddingfield, S. O'Connor, M. Yoo, M. Lee, D. Kang, S. Park, C. Zwenger, R. Darveaux, R. Lanzone, and K. Park, "Next generation fine pitch Cu Pillar technology-Enabling next generation silicon nodes", In 2011 IEEE 61st electronic components and technology conference (ECTC), 612-618 (2011).
  27. M. Huang, O. G. Yeow, C. Y. Poo, and T. Jiang, "Intermetallic Formation of Copper Pillar With Sn-Ag-Cu for Flip-Chip-On-Module Packaging," in IEEE Transactions on Components and Packaging Technologies, 31(4), 767-775 (2008). https://doi.org/10.1109/TCAPT.2008.2001194
  28. A. Yeo, W. F. Lam, and C. Lee, "Development of novel joint resistance modeling technique for flip chip interconnection systems", In 2006 Thirty-First IEEE/CPMT International Electronics Manufacturing Technology Symposium, 115-119 (2006).
  29. K. M. Chen and T. S. Lin, "Copper pillar bump design optimization for lead free flip-chip packaging", J. Mater. Sci.: Mater. Electron., 21(3), 278-284 (2010). https://doi.org/10.1007/s10854-009-9905-4
  30. O. Y. Kwon, H. S. Jung, J. H. Lee, and S. H. Choa, "Numerical Analysis of Warpage Induced by Thermo-Compression Bonding Process of Cu Pillar Bump Flip Chip Package", Trans. Korean Soc. Mech. Eng. A, 41(6), 443-453 (2017). https://doi.org/10.3795/KSME-A.2017.41.6.443
  31. Y. Orii, K. Toriyama, H. Noma, Y. Oyama, H. Nishiwaki, M. Ishida, T. Nishio, N. C. LaBianca, and C. Feger, "Ultrafine-pitch C2 flip chip interconnections with solder-capped Cu pillar bumps", In 2009 59th Electronic Components and Technology Conference, 948-953 (2009).
  32. J. H. Lau, "Recent advances and trends in advanced packaging", IEEE Trans. Compon. Packag. Manuf. Technol., 12(2), 228-252 (2022). https://doi.org/10.1109/TCPMT.2022.3144461
  33. P. T. Lee, C. H. Chang, C. Y. Lee, Y. S. Wu, C. H. Yang, and C. E. Ho, "High-speed electrodeposition for Cu pillar fabrication and Cu pillar adhesion to an Ajinomoto build-up film (ABF)", Mater. Des., 206, 109830 (2021). https://doi.org/10.1016/j.matdes.2021.109830
  34. H. Seo, H. Park, and S. E. Kim, "Cu-SiO2 Hybrid Bonding", J. Microelectron. Electron. Packag., 27(1), 17-24 (2020).
  35. L. Sun, M. H. Chen, and L. Zhang, "Microstructure evolution and grain orientation of IMC in Cu-Sn TLP bonding solder joints", J. Alloys Compd., 786, 677-687 (2019). https://doi.org/10.1016/j.jallcom.2019.01.384
  36. C. Zou, Y. Gao, B.Yang, and Q. Zhai, "Size-dependent melting properties of Sn nanoparticles by chemical reduction synthesis", Trans. Nonferrous Met. Soc. China, 20(2), 248-253 (2010). https://doi.org/10.1016/S1003-6326(09)60130-8
  37. R. Wu, X. Zhao, Y. Liu, "Atomic insights of Cu nanoparticles melting and sintering behavior in Cu-Cu direct bonding", Mater. Des., 197, 1-8 (2021).
  38. K. S. Kim, J. O. Bang, Y. H. Choa, S. B. Jung, "The characteristics of Cu nanopaste sintered by atmospheric-pressure plasma", Microelectron. Eng., 107, 121-124 (2013). https://doi.org/10.1016/j.mee.2012.08.019
  39. J. J. Li, Q. Liang, T. L. Shi, J. Fan, B. Gong, C. Feng, J. Fan, G. Liao, and Z. Tang, "Design of Cu nanoaggregates composed of ultra-small Cu nanoparticles for Cu-Cu thermocompression bonding", J. Alloys Compd., 772, 793-800 (2019). https://doi.org/10.1016/j.jallcom.2018.09.115
  40. P. Antoniammal and D. Arivuoli, "Size and Shape Dependence on Melting Temperature of Gallium Nitride Nanoparticles", J. Nanomater., 2012(8), 1-12 (2012).
  41. J. J. Ong, W. L. Chiu, O. H. Lee, C. W. Chiang, H. H. Chang, C. H. Wang, K. C. Shie, S. C. Yang, D. P. Tran, K. N. Tu, and C. Chen, "Low-Temperature Cu/SiO2 Hybrid Bonding with Low Contact Resistance Using (111)-Oriented Cu Surfaces", Mater., 15(5), 1888 (2022). https://doi.org/10.3390/ma15051888
  42. F. X. Che, H. M. Ji, H. Y. Li, and M. Kawano, "Wafer-to-wafer hybrid bonding development by advanced finite element modeling for 3-D IC packages", IEEE Trans. Compon. Packag. Manuf. Technol., 10(12), 2106-2117 (2020). https://doi.org/10.1109/TCPMT.2020.3035652
  43. G. Gao, L. Mirkarimi, T. Workman, G. Fountain, J. Theil, G. Guevara, P. Liu, B. Lee, P. Mrozek, M. Huynh, C. Rudolph, T. Werner, and A. Hanisch, "Low temperature Cu interconnect with chip to wafer hybrid bonding", In 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), 628-635 (2019).
  44. J. A. Theil, L. Mirkarimi, G. Fountain, G. Gao, and R. Katkar, "Recent developments in fine pitch wafer-to-wafer hybrid bonding with copper interconnect", In 2019 International Wafer Level Packaging Conference (IWLPC), 1-6 (2019).
  45. D. Liu, P. C. Chen, C. K. Hsiung, S. Y. Huang, Y. P. Huang, S. Verhaverbeke, G. Mori, and K. -N. Chen, "Low temperature Cu/SiO2 hybrid bonding with metal passivation", In 2020 IEEE Symposium on VLSI Technology, 1-2 (2020).
  46. R. He, M. Fujino, A. Yamauchi, Y. Wang, and T. Suga, "Combined surface activated bonding technique for low-temperature Cu/dielectric hybrid bonding", ECS J. Solid State Sci. Technol., 5(7), 419 (2016).
  47. W. L. Chiu, O. H. Lee, C. W. Chiang, and H. H. Chang, "Low-Temperature Wafer-to-Wafer Hybrid Bonding by Nano-crystalline Copper", In 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC), 679-684 (2022).
  48. Y. Beilliard, S. Moreau, L. Di. Cioccio, P. Coudrain, G. Romano, A. Nowodzinski, F. Aussenac, P. . -h. Jouneau, E. Rolland, and T. Signamarcheix, "Advances toward reliable high density Cu-Cu interconnects by Cu-SiO2 direct hybrid bonding", Proceedings of International 3D Systems Integration Conference, 1-8 (2014).
  49. I. Panchenko, L. Wambera, M. Mueller, C. Rudolph, A. Hanisch, I. Bartusseck, and M. J. Wolf, "Grain structure analysis of Cu/SiO 2 hybrid bond interconnects after reliability testing", In 2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC), 1-7 (2020).