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Thermo-Mechanical Analysis of Though-silicon-via in 3D Packaging  

Hwang, Sung-Hwan (Department of Materials Science & Engineering, Seoul National University)
Kim, Byoung-Joon (Department of Materials Science & Engineering, Seoul National University)
Jung, Sung-Yup (Department of Materials Science & Engineering, Seoul National University)
Lee, Ho-Young (Department of Materials Science & Engineering, Seoul National University)
Joo, Young-Chang (Department of Materials Science & Engineering, Seoul National University)
Publication Information
Journal of the Microelectronics and Packaging Society / v.17, no.1, 2010 , pp. 69-73 More about this Journal
Abstract
Finite-element analyses were conducted to investigate the thermal stress in 3-dimensional stacked wafers package containing through-silicon-via (TSV), which is being widely used for 3-Dimensional integration. With finite element method (FEM), thermal stress was analyzed with the variation of TSV diameter, bonding diameter, pitch and TSV height. It was revealed that the maximum von Mises stresses occurred at the edge of top interface between Cu TSV and Si and the Si to Si bonding site. As TSV diameter increased, the von Mises stress at the edge of TSV increased. As bonding diameter increased, the von Mises stress at Si to Si bonding site increased. As pitch increased, the von Mises stress at Si to Si bonding site increased. The TSV height did not affect the von Mises stress. Therefore, it is expected that smaller Cu TSV diameter and pitch will ensure mechanical reliability because of the smaller chance of plastic deformation and crack initiation.
Keywords
Through-Silicon-Via (TSV); Stacked-Wafers Package; Finite Element Analysis (FEA); Thermal Stress; Reliability;
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Times Cited By KSCI : 2  (Citation Analysis)
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