• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.15 no.7
• /
• pp.4191-4197
• /
• 2014

Value co-creation is an important business strategy these days in both the business-to-business (B2B) and business-to-consumer (B2C) markets. The aim of this study was to identify specialized resources and competences for value co-creation in the relationship network within a high-tech B2B market. A case of Taiwan Semiconductor Manufacturing Company Limited (TSMC) with customers and partners was chosen as the study case. Based on the observations, contents analysis of the secondary data and unstructured interviews with former TSMC employees, 4 critical resource types (financial, knowledge, efficiency and intellectual resource) and 6 competence types (relational, collaboration, strategic, innovation, managing and service capability), were performed as the principal factors for value co-creation in the relationship network. A research framework that can analyze the value co-creation phenomena in the relationship network was established.

• Journal of Institute of Control, Robotics and Systems
• /
• v.13 no.11
• /
• pp.1033-1039
• /
• 2007

In this paper, we design a terminal sliding mode controller based on self-recurrent wavelet neural network (SRWNN) for the second-order nonlinear systems with model uncertainties. The terminal sliding mode control (TSMC) method can drive the tracking errors to zero within finite time in comparison with the classical sliding mode control (CSMC) method. In addition, the TSMC method has advantages such as the improved performance, robustness, reliability and precision. We employ the SRWNN to approximate model uncertainties. The weights of SRWNN are trained by adaptation laws induced from Lyapunov stability theorem. Finally, we carry out simulations for Duffing system and the wing rock phenomena to illustrate the effectiveness of the proposed control scheme.

• Proceedings of the KIEE Conference
• /
• 2006.10c
• /
• pp.315-317
• /
• 2006

In this paper, we design a terminal sliding mode controller based on neural network for nonlinear systems with uncertainties. Terminal sliding mode control (TSMC) method can drive the tracking errors to zero within finite time. Also, TSMC has the advantages such as improved performance, robustness, reliability and precision by contrast with classical sliding mode control. For the control of nonlinear system with uncertainties, we employ the self-recurrent wavelet neural network(SRWNN) which is used for the prediction of uncertainties. The weights of SRWNN are trained by adaptive laws based on Lyapunov stability theorem. Finally, we carry out simulations to illustrate the effectiveness of the proposed control.

• Proceedings of the KIEE Conference
• /
• 2007.07a
• /
• pp.1642-1643
• /
• 2007

In this paper, we design a terminal sliding mode controller for chaotic nonlinear systems. Terminal sliding mode control (TSMC) method can drive the tracking errors to zero within finite time. In addition, TSMC has the advantages such as improved the performance, the robustness, the reliability and the precision by contrast with classical sliding mode control (CSMC). Besides, we can obtain the final time using general formula. Finally, we carry out simulations of some examples, such as Duffing and Lorenz systems, to illustrate the effectiveness of the proposed control.

• Electronics and Telecommunications Trends
• /
• v.37 no.2
• /
• pp.62-72
• /
• 2022

AMD is an American fabless semiconductor company that designs CPUs, GPUs, FPGAs, and APUs. AMD is competing with Intel with its Ryzen CPUs and Nvidia with its Radeon GPUs. Since 2008, production has been consigned to TSMC, concentrating on semiconductor design. AMD is releasing various new products through continuous R&D which is the basis for its growth. AMD stock have recorded the highest rise among global semiconductor companies as sales and operating profit soared due to the strong sales of new products.

• Journal of Korea Society of Industrial Information Systems
• /
• v.18 no.5
• /
• pp.9-14
• /
• 2013

This paper is designed frequency multiplier with low phase noise using DLL technique. The VCDL is designed using a differential structure to reduce common-mode noise. The proposed frequency multiplier is fabricated in a 65nm, 1.2V TSMC CMOS process, and the operating frequency range from 10MHz to 24MHz was measured. The SSB phase noise is measured to be -125dBc/Hz at 1MHz from 38.4MHz carrier. A total area of $0.032mm^2$were consumed in the chip, including the output buffer. Total current is 1.8mA at 1.2V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.1
• /
• pp.71-80
• /
• 2004

A new SSN(Simultaneous Switching Noise) model is presented, which can afford to investigate SSN due to integrated circuit package. It is shown that previous SSN models are not accurate enough to be practical since they do not take decoupling capacitor into account. In this paper, a new SSN model including the decoupling capacitor is developed. It is verified that the model has excellent agreement(within $5\%$ error) with HSPICE simulation which employs TSMC 0.18um CMOS process technology.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.17 no.2
• /
• pp.355-362
• /
• 2013

A hardware implementation of phase calculator for extracting 3D depth image from TOF(Time-Of-Flight) sensor is described. The designed phase calculator, which adopts a pipelined architecture to improve throughput, performs arctangent operation using vectoring mode of CORDIC algorithm. Fixed-point MATLAB modeling and simulations are carried out to determine the optimized bit-widths and number of iteration. The designed phase calculator is verified by FPGA-in-the-loop verification using MATLAB/Simulink, and synthesized with a TSMC 0.18-${\mu}m$ CMOS cell library. It has 16,000 gates and the estimated throughput is about 9.6 Gbps at 200Mhz@1.8V.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2008.10a
• /
• pp.112-115
• /
• 2008

In this paper, we propose H.264 High Profile Encoder Intra Prediction module. This designed module can be operated in 306 cycle for one-macroblock. To verify the Encoder architecture, we developed the reference C from JM 13.2 and verified the our developed hardware using test vector generated by reference C. We adopt plan removal and SAD calculation to reduce the Hardware cost and cycle. The designed circuit can be operated in 133MHz clock system, and has 250K gate counts using TSMC 0.18um process including SRAM memory.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2011.10a
• /
• pp.425-428
• /
• 2011

This paper presents a micro-scale solar energy harvesting circuit with a simple MPPT control. Solar Energy is harvested using a small off-chip PV cell generating output voltages under 0.5V instead of an on-chip PV cell. A simple MPPT is implemented using a pilot PV cell and utilizing the relationship between the open-circuit voltage of a PV cell ($V_{OC}$) and its MPP voltage ($V_{MPP}$). With applying the MPPT control, the designed circuit delivers the MPP voltage to load even though the loads is heavy such that the load circuit can operate properly. The proposed circuit is designed in TSMC 0.18um CMOS process.