• Title/Summary/Keyword: TCAD

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A Study on the TCAD Simulation to Predict the Latchup Immunity of High Energy Ion Implanted CMOS Twin Well Structures (고 에너지 이온 주입된 CMOS 쌍 우물 구조의 레치업 면역성 예측을 위한 TCAD 모의실험 연구)

  • 송한정;김종민;곽계달
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.13 no.2
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    • pp.106-113
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    • 2000
  • This study describes how a properly calibrated simulation method could be used to investigate the latchup immunity characteristics among the various high energy ion implanted CMOS twin well (retro-grade/BILLI/BL) structures. To obtain the accurate quantitative simulation analysis of retrograde well, a global tuning procedure and a set of grid specifications for simulation accuracy and computational efficiency are carried out. The latchup characteristics of BILLI and BL structures are well predicted by applying a calibrated simulation method for retrograde well. By exploring the potential contour, current flow lines, and electron/hole current densities at the holding condition, we have observed that the holding voltage of BL structure is more sensitive to the well design rule (p+to well edge space /n +to well edge space) than to the retrograde well itself.

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Development of integrated TCAD for VLSI process simulation (반도체 공정 시뮬레이션을 위한 통합 TCAD 개발)

  • 윤상호;이경일;공성원;이재희;원태영
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.33A no.5
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    • pp.108-116
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    • 1996
  • A semiconductor process imulator operated in windows$^{TM}$ environment has been developed. two-dimensional process simulation in personal computer has been enabled due to the improvement of CPU speed and the efficient use of memory. The process simulator in this paper is capable of calculating diffusion, oxidation, ion implantation, etching and deposition in two-dimensional manner. In addition, graphic-user-friendly editor, parser, and multi-dimensional graphical routine is also available in the devloped simulator.

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Simultaneous Fluorimetric Determination of On-line Preconcentrated HANs, DCAD and TCAD by Using RPLC with a Postcolumn Derivatization System

  • Jung, Sung-Woon;Choi, Yong-Wook
    • Bulletin of the Korean Chemical Society
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    • v.34 no.6
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    • pp.1783-1790
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    • 2013
  • A simultaneous analytical method has been developed for the fluorimetric determination of haloacetonitriles (HANs) [dichloroacetonitrile (DCAN), trichloroacetonitrile (TCAN), dibromoacetonitrile (DBAN), haloacetamides [dichloroacetamide (DCAD), and trichloroacetamde (TCAD)] in drinking water by using the combined on-line perconcentration/reversed phase liquid chromatography (RPLC)-postcolumn detection system. This on-line perconcentration system was achieved by employing a precolumn packed with a commercial solid phase extraction (SPE) sorbent for the enrichment and purification of the target analytes. The haloacetonitriles and haloacetamides were separated on CN analytical column in a 7.5% methanol-0.02 M phosphate buffered mobile phase at pH 3. The column effluents were reacted with postcolumn reagents of ophthaldialdehyde (OPA) and sulfite ion at pH 11.5, to produce a highly fluorescent isoindole fluorophore, which were measured with a fluorescence detector. Under the optimized conditions for RPLC and the postcolumn derivatization system all of the coefficient of determination of the standard calibration curves for the target analytes were over 0.99 and had a linear range from 5 to 100 ${\mu}g/L$. The detection limits showed 1.6 ${\mu}g/L$ for DCAD, 0.1 ${\mu}g/L$ for TCAD, 0.6 ${\mu}g/L$ for DCAN, 1.6 ${\mu}g/L$ for TCAN and 1 ${\mu}g/L$ for DBAN, and the recoveries were ranged from 64 to 99% except for DCAD with precisions less than 4.9% in distilled water, and from 72(${\pm}4%$) to 116%(${\pm}2%$) in tap water.

A study on the pinch-off characteristics for Double Cate MOSFET in nuo structure (나노 구조 Double Gate MOSFET의 핀치오프특성에 관한 연구)

  • 고석웅;정학기
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.6 no.7
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    • pp.1074-1078
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    • 2002
  • In this paper, we designed double gate(DG) MOSFET structure which has main gate(MG) and two side gates(SG). We have simulated using TCAD simulator U .WOSFET have the main gate length of %m and the side gate length of 70nm. Then, u'e have investigated the pinch-off characteristics, drain voltage is changed from 0V to 1.5V at VMG=1.5V and VSG=3.0V. In spite of the LMG is very small, we have obtained a very good pinch-off characteristics. Therefore, we know that the DG structure is very useful at nano scale.

Breakdown Voltage Characteristics of LDMOST with External Field Ring (외부 전계 링을 갖는 LDMOST의 항복전압 특성)

  • Oh Dong-joo;Yeom Kee-soo
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.8 no.8
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    • pp.1719-1724
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    • 2004
  • In this paper, we have proposed a new structure of LDMOST, which has been expected as a next generation RF power device, to improve the BV(Breakdown Voltage) characteristics. The proposed structure, named external field ring, is formed around a drift region by the three dimensional structure. The external field ring relieves the electric field in the drift region and improves the BV characteristics. By the three dimensional TCAD simulations, it was found that the BV of LDMOST was increased by the increase of the junction depth and doping concentration of the external field ring. Therefore, the BV characteristics of the LDMOST can be remarkably improved by addition of external field ring using an existing p+ sinker process.

The Short Channel Effect Immunity of Silicon Nanowire SONOS Flash Memory Using TCAD Simulation

  • Yang, Seung-Dong;Oh, Jae-Sub;Yun, Ho-Jin;Jeong, Kwang-Seok;Kim, Yu-Mi;Lee, Sang Youl;Lee, Hi-Deok;Lee, Ga-Won
    • Transactions on Electrical and Electronic Materials
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    • v.14 no.3
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    • pp.139-142
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    • 2013
  • Silicon nanowire (SiNW) silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices were fabricated and their electrical characteristics were analyzed. Compared to planar SONOS devices, these SiNW SONOS devices have good program/erase (P/E) characteristics and a large threshold voltage ($V_T$) shift of 2.5 V in 1ms using a gate pulse of +14 V. The devices also show excellent immunity to short channel effects (SCEs) due to enhanced gate controllability, which becomes more apparent as the nanowire width decreases. This is attributed to the fully depleted mode operation as the nanowire becomes narrower. 3D TCAD simulations of both devices show that the electric field of the junction area is significantly reduced in the SiNW structure.

Dynamic Self-Heating Effects of Bulk and SOI FinFET with Realistic Device Structure (실제적 구조를 가진 벌크 및 SOI FinFET에서 발생하는 동적 self-heating 효과)

  • Ryu, Heesang;Chung, Hayun Cecillia;Yang, Ji-Woon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.52 no.10
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    • pp.64-69
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    • 2015
  • Self-heating effects of bulk and SOI FinFETs on device structure are examined with TCAD simulation. The degradation of drive current in SOI FinFET is severer than that of bulk one in steady-state condition as expected. However, it is shown that the dynamic self-heating effects of SOI FinFETs are comparable to those of bulk FinFETs for high speed logic operation, especially in realistic device structure.

Impacts of Trapezoidal Fin of 20-nm Double-Gate FinFET on the Electrical Characteristics of Circuits

  • Ryu, Myunghwan;Kim, Youngmin
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.15 no.4
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    • pp.462-470
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    • 2015
  • In this study, we analyze the impacts of the trapezoidal fin shape of a double-gate FinFET on the electrical characteristics of circuits. The trapezoidal nature of a fin body is generated by varying the angle of the sidewall of the FinFET. A technology computer-aided-design (TCAD) simulation shows that the on-state current increases, and the capacitance becomes larger, as the bottom fin width increases. Several circuit performance metrics for both digital and analog circuits, such as the fan-out 4 (FO4) delay, ring oscillator (RO) frequency, and cut-off frequency, are evaluated with mixed-mode simulations using the 3D TCAD tool. The trapezoidal nature of the FinFET results in different effects on the driving current and gate capacitance. As a result, the propagation delay of an inverter decreases as the angle increases because of the higher on-current, and the FO4 speed and RO frequency increase as the angle increases but decrease for wider angles because of the higher impact on the capacitance rather than the driving strength. Finally, the simulation reveals that the trapezoidal angle range from $10^{\circ}$ to $20^{\circ}$ is a good tradeoff between larger on-current and higher capacitance for an optimum trapezoidal FinFET shape.

The Effect of Blocking Layer Design Variable on the Characteristics of GaN-based Light-Emitting Diode (차단층 설계 변수가 GaN 기반 LED 특성에 미치는 영향)

  • Lee, Jae-Hyun;Yeom, Keesoo
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2012.10a
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    • pp.233-236
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    • 2012
  • In this paper, the output characteristics of GaN-based LED considering blocking layer design variables are analyzed. The basic structure of the LED consists of active region of GaN barrier and InGaN quantum well between AlGaN EBL(Electron Blocking Layer) and AlGaN HBL(Hole Blocking Layer) on GaN buffer layer. The output power, internal quantum efficiency characteristics of LED active region considering Al mole fraction of EBL, thickness of EBL, Al mole fraction of HBL and doping concentration of HBL are analyzed using ISE-TCAD.

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The Effect of Quantum Well Structure on the Characteristics of GaN-based Light-Emitting Diode (양자 우물 구조가 GaN 기반 LED 특성에 미치는 영향)

  • Lee, Jae-Hyun;Yeom, Keesoo
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2012.10a
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    • pp.251-254
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    • 2012
  • In this paper, the output characteristics of GaN-based LED considering quantum well structure are analyzed. The basic structure of the LED consists of active region of GaN barrier and InGaN quantum well between AlGaN EBL(Electron Blocking Layer) and AlGaN HBL(Hole Blocking Layer) on GaN buffer layer. The output power, internal quantum efficiency characteristics of LED active region considering thickness of quantum well, number of quantum well and doping of barrier are analyzed using ISE-TCAD.

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