• JSTS:Journal of Semiconductor Technology and Science
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• 제4권2호
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• pp.117-123
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• 2004

A 30 nm $In_{0.7}GaAs$ High Electron Mobility Transistor (HEMT) with triple-gate has been successfully fabricated using the $SiO_2/SiN_x$ sidewall process and BCB planarization. The sidewall gate process was used to obtain finer lines, and the width of the initial line could be lessened to half by this process. To fill the Schottky metal effectively to a narrow gate line after applying the developed sidewall process, the sputtered tungsten (W) metal was utilized instead of conventional e-beam evaporated metal. To reduce the parasitic capacitance through dielectric layers and the gate metal resistance ($R_g$), the etchedback BCB with a low dielectric constant was used as the supporting layer of a wide gate head, which also offered extremely low Rg of 1.7 Ohm for a total gate width ($W_g$) of 2x100m. The fabricated 30nm $In_{0.7}GaAs$ HEMTs showed $V_{th}$of -0.4V, $G_{m,max}$ of 1.7S/mm, and $f_T$ of 421GHz. These results indicate that InGaAs nano-HEMT with excellent device performance could be successfully fabricated through a reproducible and damage-free sidewall process without the aid of state-of-the-art lithography equipment. We also believe that the developed process will be directly applicable to the fabrication of deep sub-50nm InGaAs HEMTs if the initial line length can be reduced to below 50nm order.

• Journal of Electrical Engineering and Technology
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• 제1권2호
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• pp.237-240
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• 2006

The feasibility of a midgap metal gate is investigated for a 32 nm MOSFET for low power applications. The midgap metal gate MOSFET is found to deliver $I_{on}$ as high as a bandedge gate if a proper retrograde channel is used. An adequate design of the retrograde channel is essential to achieve the performance requirement given in the ITRS roadmap. A process simulation is also run to evaluate the feasibility of the necessary retrograde profile in manufacturing environments. Based on the simulated result, it is found that any subsequent thermal process should be tightly controlled to retain transistor performance, which is achieved using the retrograde doping profile. Also, the bandedge gate MOSFET is determined be more vulnerable to the subsequent thermal processes than the midgap gate MOSFET. A guideline for gate workfunction $(\Phi_m)$ is suggested for the 32 nm MOSFET.

• 대한전기학회논문지
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• 제43권2호
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• pp.244-250
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• 1994

This paper presents the design of a new turn-off gate drive circuit for GTO which can accomplish faster turn-off switching. The major disadvantage of the conventional turn-off gate drive technique is that it has a difficulty in realizing high negative diS1GQT/dt because of VS1RGM(maximum reverse gate voltage) and stray inductances of turn-off gate drive circuit[1~2]. The new trun-off gate drive technique can overcome this problem by adding another turn-off gate drive circuit to the conventional turn-off gate drive circuit. Simulation and experimental results of the new turn-off gate drive circuit in conjunction with chopper circuit verify a faster turn-off switching performance.

• 한국해양공학회지
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• 제5권1호
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• pp.64-70
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• 1991

The design theory of roller gate has been systematized laying more emphasis on practical formulas than theoretical ones and the design procedure of the existing gate facilites is reviewed and analyaed on economical viewpoint and safety factor. The design theory of timoshenko, the thechnical standards for hydraulic gate and penstock of Japan, and the design standards for waterworks structures of Germany are applied to the study of optimal design of a gate leaf. In this study, gate leaf which is now being operated for water control at the seadike, estuary dam and reservoir dam are adopted as a mode, and a new design method by the computer is proposed through the variation of design elements within practical ranges. As a result, safety factor and economical design can be made by using T-beams to the horizontal and vertical beam of the gate leaf instead of H-beams used in the existing seadike roller gate at Asan, and total weight of gate leaf is reduced by the present optimization.

• Journal of Electrical Engineering and information Science
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• 제2권3호
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• pp.132-138
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• 1997

Electrical characteristics of split-gate flash EEPROM with triple polysilicon is investigated in terms of effects of floating gate and offset gate. In order to search for t the effects of offset gate on programming characteristics, threshold voltage and drain current are studied with variation of control gate voltage. The programming process is believed to depend on vertical and horizontal electric field as well as offset gate length. The erase and program threshold voltage are found to be almost constant with variation of control gate voltage above 12V, while endurance test indicates degradation of program threshold voltage. With increase of offset gate length, program threshold voltage becomes smaller and the drain source voltage just after program under constant control gate voltage becomes higher.

• ETRI Journal
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• 제18권3호
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• pp.171-179
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• 1996

Fully passivated low noise AlGaAs/InGaAs/GaAs pseudomorphic (PM) HEMT with wide head T-shaped gates were fabricated by dose split electron beam lithography (DSL). The dimensions of gate head and footprint were optimized by controlling the splitted pattern size, dose, and spaces of each pattern. We obtained stable T-shaped gate of $0.15{\mu}m$ gate length with $1.35{\mu}m-wide$ head. The maximum extrinsic transconductance was 560 mS/mm. The minimum noise figure measured at 18 GHz at $V_{ds}=2V andI_{ds}=17mA$ was 0.41 dB with associated gain of 8.19 dB. At 12 GHz, the minimum noise figure and an associated gain were 0.26 and 10.25 dB, respectively. These noise figures are the lowest values ever reported for GaAs-based HEMTs. These results are attributed to the extremely low gate resistance of wide head T-shaped gate having a ratio of the head to footprint dimensions larger than 9.

• 문화기술의 융합
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• 제7권1호
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• pp.558-563
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• 2021

양자점 셀룰라 오토마타(Quantum-Dot Cellular Automata)는 기존의 CMOS 회로의 물리적 크기 한계를 극복하여 효율적인 회로 설계가 가능할 뿐만 아니라 에너지 효율이 우수한 특징 때문에 많은 연구 단체에서 주목받고 있는 차세대 나노 회로 설계기술이다. 본 논문에서는 QCA를 이용하여 기존 디지털 회로 중 하나인 T 플립플롭 회로를 제안한다. 기존에 제안되었던 T 플립플롭들은 다수결게이트를 기반으로 설계되었기 때문에 회로가 복잡하며 지연시간이 길다. 따라서 다수결게이트를 최소화시키며, 셀 간 상호작용을 이용한 XOR 게이트 기반의 T 플립플롭을 설계함으로써 회로의 복잡도를 줄이고, 지연시간을 최소화한다. 제안하는 회로는 QCADesigner를 사용하여 시뮬레이션을 진행하며, 기존에 제안된 회로들과 성능을 비교 및 분석한다.

• 한국전기전자재료학회논문지
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• 제30권2호
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• pp.63-66
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• 2017

This research was about shielded trench gate power MOSFET for low voltage and high speed. We used T-CAD tool and carried out process and device simulation for exracting design and process parameters. The exracted parameters was used to design shieled and conventional trench gate power MOSFET. And The electrical characteristics of shieled and conventional trench gate power MOSFET were compared and analyzed for their power device applications. As a result of analyzing electrical characteristics, the recorded breakdown voltages of both devices were around 120 V. The electric distributions of shielded and conventional trench gate power MOSFET was different. But due to the low voltage level, the breakdown voltage was almost same. And the other hand, the threshold voltage characteristics of shielded trench gate power MOSFET was superior to convention trench gate power MOSFET. In terms of on resistance characteristics, we obtained optimal oxied thickness of $3{\mu}m$.

• 한국자기학회지
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• 제22권2호
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• pp.45-48
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• 2012

Co계 비정질 리본인 Metglass$^{(R)}$2714A 코어를 사용하여, 자기장 측정 범위가 ${\pm}100\;{\mu}T$, 측정 주파수 범위가 dc~10 Hz인 3-축의 피드백형 플럭스게이트 마그네토미터를 제작하였다. 제작된 마그네토미터의 아날로그 출력의 전기잡음은 5 pT/$\sqrt{Hz}$ at 1 Hz 이었으며, Micro-controller와 24 bit ADC(Analog to Digital Converter)를 사용한 마그네토미터의 출력을 0.1 nT의 분해능으로 디지털로 출력 할 수 있게 하였다. 디지털 신호로 출력되는 마그네토미터의 선형도는 $1{\times}10^{-4}$ 이하였으며, 1시간 동안 영점 변화는 0.2 nT 이하였다.

• 한국항행학회논문지
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• 제23권2호
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• pp.207-213
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• 2019

최근 IoT 산업에서 보안의 중요성이 증가하고 있으며, IoT (internet of things) 통신 산업에서는 소형의 하드웨어 칩이 필요하다. 이를 위해 본 논문에서는 대표적인 블록 암호 알고리즘인 AES (advanced encryption standard), ARIA (academy, research, institute, agency)와 CLEFIA를 통합한 저면적 암호화 프로세서를 제안한다. 제안하는 암호화 프로세서는 128 비트 기반으로 라운드 키 생성 과정과 암호화 및 복호화 과정을 하나로 공유하였으며, 각각 알고리즘의 구조를 공유 시켜 면적을 축소하였다. 더불어, 경량 IoT 기기를 포함한 대부분의 IoT 기기나 시스템에 적용이 가능하도록 구현하였다. 본 프로세서는 Verilog HDL (hardware description language)로 기술되었고65nm CMOS 공정을 통해 논리 합성하여 11,080개의 논리 게이트로 구현 가능함을 확인하였다. 결과적으로 각 알고리즘 개별 구현 대비 gate 수 총계에서 약42%의 이점을 보인다.