• Journal of IKEEE
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• v.7 no.1 s.12
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• pp.56-62
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• 2003

In this paper, we designed a adder and a multiplier using current mode T-gate on $GF(2^2)$. The T-gate is consisted of current mirror and pass transistor, the designed 4-valued T-gate used adder and multiplier on $GF(2^2)$. We designed its under 1.5um CMOS standard technology. The unit current of the circuits is 15㎂, and power supply is 3.3V VDD. The proposed current mode CMOS operator have a advantage of module by T-gate`s arrangement, and so we easily implement multi-valued operator.

• Journal of the Korean Magnetics Society
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• v.12 no.4
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• pp.149-153
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• 2002

Flux-gate magnetometer has been still used for low field magnetic field measurement with portability, low power consumption, and high reliability. In many applications, flux-gate magnetometer measures not absolute values but changes of the earth magnetic field. For the eia magnetic field change measurements, we have constructed a high sensitive 3-axis flux-gate magnetometer of which measuring ranges is ${\pm}$1000 nT and noise level is 5pT/√㎐ at 1 ㎐. Using this magnetometer, we can compensate the earth magnetic field of ${\pm}$50,000 nT with successive approximation methods using microcomputer. After earth magnetic field compensation, we could measure earth magnetic field changes with ${\pm}$100 nT measuring ranges.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.2
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• pp.134-142
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• 2010

A comparative study on the trade-off between the drive current and the total gate capacitance in double-gate (DG) and triple-gate (TG) FinFETs is performed by using 3-D device simulation. As the first result, we found that the optimum ratio of the hardmask oxide thickness ($T_{mask}$) to the sidewall oxide thickness ($T_{ox}$) is $T_{mask}/T_{ox}$=10/2 nm for the minimum logic delay ($\tau$) while $T_{mask}/T_{ox}$=5/1~2 nm for the maximum intrinsic gate capacitance coupling ratio (ICR) with the fixed channel length ($L_G$) and the fin width ($W_{fin}$) under the short channel effect criterion. It means that the TG FinFET is not under the optimal condition in terms of the circuit performance. Second, under optimized $T_{mask}/T_{ox}$, the propagation delay ($\tau$) decreases with the increasing fin height $H_{fin}$. It means that the FinFET-based logic circuit operation goes into the drive current-dominant regime rather than the input gate load capacitance-dominant regime as $H_{fin}$ increases. In the end, the sensitivity of $\Delta\tau/{\Delta}H_{fin}$ or ${{\Delta}I_{ON}}'/{\Delta}H_{fin}$ decreases as $L_G/W_{fin}$ is scaled-down. However, $W_{fin}$ should be carefully designed especially in circuits that are strongly influenced by the self-capacitance or a physical layout because the scaling of $W_{fin}$ is followed by the increase of the self-capacitance portion in the total load capacitance.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.187-190
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• 1999

We have developed fabrication processes that form a wide-head T-gate with a 0.2 ${\mu}{\textrm}{m}$ gate length using the combination of thickness of each PMMA layer, line doses and development times for applications in millimeter- and micro-waves monolithic integrated circuits. The three-layer resist structure (PMMA/P(MMA-MAA)/PMMA = 1800 $\AA$/5800 A/1900$\AA$), 4nC/cm and over development were used for fabrication of a wide-head T-gate by the conventional double E-beam exposure technology. The experimented results show that the cross sectional area of T-gate fabricated by the proposed method is easily enlarged without additional processes.

• Journal of electromagnetic engineering and science
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• v.13 no.2
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• pp.127-133
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• 2013

We examined the scaling effects of a number of gate_fingers (N) and gate_widths (w) on the high-frequency characteristics of $0.1-{\mu}m$ metamorphic high-electron-mobility transistors. Functional relationships of the extracted small-signal parameters with total gate widths ($w_t$) of different N were proposed. The cut-off frequency ($f_T$) showed an almost independent relationship with $w_t$; however, the maximum frequency of oscillation ($f_{max}$) exhibited a strong functional relationship of gate-resistance ($R_g$) influenced by both N and $w_t$. A greater $w_t$ produced a higher $f_{max}$; but, to maximize $f_{max}$ at a given $w_t$, to increase N was more efficient than to increase the single gate_width.

• 전자공학회논문지 IE
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• v.47 no.1
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• pp.1-5
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• 2010

This paper presents new results of the impact of gate structure on hot-carrier-induced performance degradation in SOI low noise amplifier. Circuit simulations were carried out using the measured S-parameters of H--gate and T-gate SOI MOSFETs and Agilent's Advanced Design System (ADS) to compare the performance of H-gate LNA and T-gate LNA before and after stress. We will discuss the figure of merit for the characterization of low noise amplifier in terms of impedance matching (S11), noise figure, and gain as well as the relation between device degradation and performance degradation of LNA.

• Proceedings of the KIEE Conference
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• 1999.07d
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• pp.1965-1967
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• 1999

We have investigated the electrical characteristics of the poly-Si TFT's with the novel gate insulator structure. The gate insulator makes the offset region to reduce leakage current, and the electrical characteristics are obtained by employing Virtual Wafer Fab. simulator. As increases the gate insulator thickness above the offset region of this structure from $0{\AA}$ to $2000{\AA}$, the OFF state current at $V_G$=10V decrease by two orders in magnitude while ON state current doesn't decrease significantly. ON/OFF current ratios for conventional device and the proposed device with $2000{\AA}$ gate insulator thickness are $1.68{\times}10^5$ and $1.07{\times}10^7$, respectively.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.8
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• pp.72-80
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• 1993

We fabricated 0.3um gate length inverse-T gate MOS(ITMOS) and conventional lightly doped drain oxide spacer MOS(LDDMOS), and studied electrical characteristics for comparison. Threshold voltage of 0.3um gate length device was 0.58 V for ITMOS and 0.6V for LDDMOS. Measured subthreshold characteristics showed a slope of 85mV/decades for both ITLDD and LDDMOS. Maximum transconductance at V S1ds T=V S1gs T=3.3V was 180mS/mm for ITMOS and 163mS/mm for LDDMOS respectively. GIDL current was observed to be 0.1pA/um for ITOMS and 0.8pA/um for LDDMOS. Substrate current of ITMOS as a function of drain current was found to be reduced by a foactor of 2.5 compared with that of LDDMOS.

• Proceedings of the KIEE Conference
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• 1998.07d
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• pp.1315-1317
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• 1998

We have investigated the effects of electrical stress on poly-Si TFTs with different hydrogen passivation conditions. The amounts of threshold voltage shift of hydrogen passivated poly-Si TFTs are much larger than those of as-fabricated devices both under the gate bias stressing and under the gate and drain bias stressing. Also, we have quantitatively analized the degradation phenomena using by analytical method. we have suggested that the electron trapping in the gate dielectric is the dominant degradation mechanism in only gate bias stressed poly-Si TFT while the creation of defects in the poly-Si is prevalent in gate and drain bias stressed device.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.5
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• pp.23-36
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• 2004

A computationally efficient and accurate Monte Carlo (MC) simulator of electron beam lithography process has been developed for sub-0.l${\mu}{\textrm}{m}$ T-shaped gate formation in the HEMT devices for millimeter-wave frequencies. For the exposure process by electron to we newly and efficiently modeled the inner-shell electron scattering and its discrete energy loss with an incident electron for multi-layer resists and heterogeneous multi-layer targets in the MC simulation. In order to form the T-gate shape in resist layers, we usually use the different developer for each resist layer to obtain good reproducibility in the fabrication of HEMT devices. To model accurately the real fabrication process of electron beam lithography, we have applied the different developers in trilayer resist system By using this model we have simulated and analyzed 0.l${\mu}{\textrm}{m}$ T-gate fabrication process in the HEMT devices, and showed our simulation results with the SEM observations of the T-shaped gate process.