References
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- IEICE Trans. Electron v.E76-C no.3 Prospects of Multiple-Valued VLSI Processors T. Hanyu;M. Kameyama;T. Higuchi
- COMP. mag. Multiple-valued logic : A Tutorial and Appreciation K. C. Smith
- IEEE Trans. Comput. v.C-25 no.1 Galois switching functions and their application B.Benjauthrit;I. S. Reed
- IEEE Trans. Comput. v.C-18 no.3 A transform logic networks K. S. Menger
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IEEE Trans. Comput.
v.C-34
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VLSI architectures for computing multiplications and inverses in GF(
$2^{m}$ ) C. C. Wang;T. K. Truong;H. M. Shao;L. J. Deutsch;J. K. Omura;I. S. Reed - IEEE Trans. Comput. v.C-34 no.5 A VLSI design of a pipelining Reed-solomon decoder H. M. Shao;T. K. Truong;L. J. Deutch;J. H. Yaeh;I. S. Reed
- Proc. 23th ISMVL Current-mode CMOS Galois field circuits Z. Zilic;Z. Vranesic
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- ISMVL 30th Demonstration of a novel multiple-valued T-gate using multiple-junction surface tunnel transistors and its application to three-valued data flip-flop T. Uemura;T. Baba