• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.22-28
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• 2008

This paper designed a efficient 8-bit CMOS analog-to-digital converter(ADC) for an SOC(System On Chip) application. The architecture consists of two modified 4-bit full-flash ADCs, it has been designed using a more efficient architecture. This is to predict roughly the range in which input signal residers and can be placed in the proximity of input signal based on initial prediction. The prediction of input signal is made available by introducing a voltage estimator. For 4-bit resolution, the modified full-flash ADC need only 6 comparators. So a 8-bit ADC require only 12 comparators and 32 resistors. The speed of this ADC is almost similar to conventional full-flash ADC, but the die area consumption is much less due to reduce numbers of comparators and registors. This architecture uses even fewer comparator than half-flash ADC. The circuits which are implemented in this paper is simulated with LT SPICE tool of computer.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.29 no.10 s.241
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• pp.1289-1297
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• 2005

The flow in a microchannel is usually characterized as a low Reynolds number (Re) so that good mixing is quite difficult to be achieved. In this regard, we developed a novel chaotic micromixer, named Serpentine Laminating Micromixer (SLM) in the present study, Part 1. In the SLM, the higher level of chaotic mixing can be achieved by combining two general chaotic mixing mechanisms: splitting/recombination and chaotic advection. The splitting and recombination (in other term, lamination) mechanism is obtained by the successive arrangement of 'F'-shape mixing units in two layers. The chaotic advection is induced by the overall three-dimensional serpentine path of the microchannel. Chaotic mixing performance of the SLM was fully characterized numerically. To compare the mixing performance, a T-type micromixer which has the same width, height and length of the SLM was also designed. The three-dimensional numerical mixing simulations show the superiority of the SLM over the T-type micromixer. From the cross-sectional simulation results of mixing patterns, the chaotic advection effect from the serpentine channel path design acts favorably to realize the ideal lamination of fluid flow as Re increases. Chaotic mixing mechanism, proposed in this study, could be easily integrated in Micro-Total-Analysis-System, Lab-on-a-Chip and so on.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.29 no.10 s.241
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• pp.1298-1306
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• 2005

In this paper, Part II, we realized the Serpentine Laminating Micromirer (SLM) which was proposed in the accompanying paper, Part I, by means of the injection molding process in mass production. In the SLM, the higher level of chaotic mixing can be achieved by combining two general chaotic mixing mechanisms of splitting/recombination and chaotic advection by the successive arrangement of 'F'-shape mixing units in two layers. Mold inserts for the injection molding process of the SLM were fabricated by SU-8 photolithography and nickel electroplating. The SLM was realized by injection molding of COC (cyclic olefin copolymer) with the fabricated mold inserts and thermal bonding of two injection molded COC substrates. To compare the mixing performance, a T-type micromixer was also fabricated. Mixing performances of micromixers were experimentally characterized in terms of an average mixing color intensity of a pH indicator, phenolphthalein. Experimental results show that the SLM has much better mixing performance than the I-type micromixer and chaotic mixing was successfully achieved from the SLM over the wide range of Reynolds number (Re). The chaotic micromixer, SLM proposed in this study, could be easily integrated in Micro-Total-Analysis- System , Lab-on-a-Chip and so on.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.4
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• pp.25-34
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• 2000

In this paper, we first investigate the effect of residual code phase offset on the DS/CDMA code acquisition scheme. When the code phase offset normalized to the chip duration is within the advancing step size, the sum of two successive matched filter outputs has a constant value regardless of the residual code phase offset if noise is absent. Based on this observation, we propose a new code acquisition scheme, and investigate the performance of the scheme. The Proposed code acquisition scheme is analyzed, and numerical results are given to show that the proposed scheme is more robust to the variation of the residual code phase offset and has better performance than the conventional scheme.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.4
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• pp.826-832
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• 2004

A CMOS 8 bit folding and interpolating ADC for an embedded system inside VLSI is presented in this paper. This folding ADC uses the 2 stage architecture for improving of nonlinearity. repeating the folding and interpolating twice. At a proposed structure, a transistor differential pair operates on the second folder. A ADC with 2 stage architecture reduces the number of comparators and resisters. So it is possible to provide small chip size, low power consumption and high operating speed. The design technology is based on fully standard 0.25m double-Poly 2 metal n-well CMOS Process. The simulated Power consumption is 45mW with an applied voltage of 2.5V and sampling frequency of 250MHz. The INL and DNL are within <ㅆㄸㅌ>$\pm$0.2LSB, respectively. The SNDR is approximately 45dB for input frequency of 10MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.1
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• pp.14-24
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• 2002

In this paper, a design of the pulsewidth-modulation(PWM) neural network with both retrieving and learning function is proposed. In the designed PWM neural system, the input and output signals of the neural network are represented by PWM signals. In neural network, the multiplication is one of the most commonly used operations. The multiplication and summation functions are realized by using the PWM technique and simple mixed-mode circuits. Thus, the designed neural network only occupies the small chip area. By applying some circuit design techniques to reduce the nonideal effects, the designed circuits have good linearity and large dynamic range. Moreover, the delta learning rule can easily be realized. To demonstrate the learning capability of the realized PWM neural network, the delta learning nile is realized. The circuit with one neuron, three synapses, and the associated learning circuits has been designed. The HSPICE simulation results on the two learning examples on AND function and OR function have successfully verified the function correctness and performance of the designed neural network.

• The KIPS Transactions:PartB
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• v.10B no.7
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• pp.815-822
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• 2003

Fingerprint image enhancement and minutiae matching are two key steps in an automatic fingerprint identification system. In this paper, we propose a fingerprint recognition technique by using minutiae linking information. Recognition process have three steps ; preprocessing, minutiae extraction, matching step based on minutiae pairing. After extracting minutiae of a fingerprint from its thinned image for accuracy, we introduce matching process using minutiae linking information. Introduction of linking information into the minutiae matching process is a simple but accurate way, which solves the problem of reference minutiae pair selection with low cost in comparison stage of two fingerprints. This algorithm is invariable to translation and rotation of fingerprint. The matching algorithm was tested on 500 images from the semiconductor chip style scanner, experimental result revealed the false acceptance rate is decreased and genuine acceptance rate is increased than existing method.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.520-523
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• 2016

This paper describes a DC-DC converter with MPPT control for thermoelectric energy harvesting. The designed circuit converts low voltage harvested from a thermoelectric generator into higher voltage for powering a load. A start-up circuit supplies VDD to a controller, and the controller turns on and off a NMOS switch of a main-boost converter. The converter supplies the boosted voltage to the load through the switch operation. Bulk-driven comparators can do the comparison under low voltage condition and are used for voltage regulation. Also, bulk-driven comparators raise system's efficiency. A peak conversion efficiency of 76% is achieved. The proposed circuit is designed in a 0.35um CMOS technology and its functionality has been verified through simulations. The designed chip occupies $933um{\times}769um$.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.18 no.7
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• pp.56-62
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• 2019

The high-precision laser scriber carries out scribing alumina ceramic substrates for manufacturing ultra-small chip resistors. The ceramic substrates are loaded, aligned, scribed, transferred, and unloaded. The entire process is fully automated, thereby minimizing the scribing cycle time of the ceramic substrates and improving the throughput. The scriber consists of the laser optical system, pick-up module of ceramic substrates, pre-alignment module, TH axis drive work table, automation module for substrate loading / unloading, and high-speed scribing control S/W. The loader / unloader unit, which has the greatest influence on the scribing cycle time of the substrates, carries the substrates to the work table that carries out the cutting line work by driving the X and Y axes as well as by adsorbing the ceramic substrates. The loader / unloader unit consists of the magazine up / down part, X-axis drive part for conveying the substrates to the left and right direction, and the vision part for detecting the edge of the substrate for the primary pre-alignment of the substrates. In this paper, the laser scribing machining simulation is performed by applying the instrument mechanism of each component module. Through this study, the scribing machining process is first verified by analyzing the process operation and work area of each module in advance. In addition, the scribing machining process is optimized by comparing and analyzing the scribing cycle time of one ceramic substrate according to the alignment stage module speed.

• Nuclear Engineering and Technology
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• v.54 no.7
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• pp.2444-2452
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• 2022

The field-programmable gate array (FPGA) is gaining popularity in industrial automation such as nuclear power plant instrumentation and control (I&C) systems due to the benefits of having non-existence of operating system, minimum software errors, and minimum common reason failures. Separate functions can be processed individually and in parallel on the same integrated circuit using FPGAs in comparison to the conventional microprocessor-based systems used in any plant operations. The use of FPGAs offers the potential to minimize complexity and the accompanying difficulty of securing regulatory approval, as well as provide superior protection against obsolescence. Wireless sensor networks (WSNs) are a new technology for acquiring and processing plant data wirelessly in which sensor nodes are configured for real-time signal processing, data acquisition, and monitoring. ZigBee (IEEE 802.15.4) is an open worldwide standard for minimum power, low-cost machine-to-machine (M2M), and internet of things (IoT) enabled wireless network communication. It is always a challenge to follow the specific topology when different Zigbee nodes are placed in a large network such as a plant. The research article focuses on the hardware chip design of different topological structures supported by ZigBee that can be used for monitoring and controlling the different operations of the plant and evaluates the performance in Vitex-5 FPGA hardware. The research work presents a strategy for configuring FPGA with ZigBee sensor nodes when communicating in a large area such as an industrial plant for real-time monitoring.