• Journal of Electrical Engineering and information Science
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• 제2권3호
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• pp.14-21
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• 1997

In delay-optimized designs, timing failures due to manufacturing delay defects are more likely to occur because the average timing slacks of paths decrease and the system becomes more sensitive to smaller delay defect sizes. In this paper, the impact of delay optimized logic circuits on delay fault testing will be discussed and compared to the case for non-optimized designs. First, we provide a timing optimization procedure and show that the resultant density function of path delays is a delta function. Next we also discuss the impact of timing optimization on the yield of a manufacturing process and the defect level for delay faults. Finally, we will give some recommendations on the determination of the system clock time so that the delay-optimized design will have the same manufacturing yield as the non-optimized design and on the determination of delay fault coverage in the delay-optimized design in order to have the same defect-level for delay faults as the non-optimized design, while the system clock time is the same for both designs.

• 산업경영시스템학회지
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• 제22권53호
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• pp.89-97
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• 1999

We are concerned with the optimal design of flexible manufacturing cells in this study, thus try to suggest the detail information for each resource on the optimal conditions. Object oriented simulation technology is used to write models more easily and to execute simulation running time more rapidly, and the optimal level of relevant decision variables is probed by response surface methodology(RSM), which is well known for the optimization technology based on experiment design and regression equation. We investigate the optimal level for the number of pallets and the speed of AGVs of FMC systems, carry out the performance analysis of this system. Consequently we suggest systematic procedures for the optimization of FMCs in detail design stage.

• 한국지능정보시스템학회:학술대회논문집
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• 한국지능정보시스템학회 2001년도 The Pacific Aisan Confrence On Intelligent Systems 2001
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• pp.211-218
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• 2001

This paper introduces a method of constructing expert systems in an integrated environment for automatic software design. This integrated environment may be applicable from top-level system architecture design, data flow diagram design down to flow chart and coding. The system is integrated with three CASE tools, FSD (Functional Structure Diagram), DFD (Data Flow Diagram) and structured chart PAD (Problem Analysis Diagram), and respective expert systems with automatic design capability by reusing past design. The construction way of these expert systems is based on systematic acquisition of design knowledge stemmed from a systematic design work process of well-matured developers. The design knowledge is automatically acquired from respective documents and stored in the respective knowledge bases. By reusing it, a similar software system may be designed automatically. In order to develop these expert systems in a short period, these design knowledge is expressed by the unified frame structure, functions of th expert system units are partitioned mono-functions and then standardized components. As a result, the design cost of an expert system can be reduced to standard work procedures. Another feature of this paper is to introduce the integrated environment for automatic software design. This system features an essentially zero start-up cost for automatic design resulting in substantial saving of design man-hours in the resulting in substantial saving of design man-hours in the design life cycle, and the expected increase in software productivity after enough design experiences are accumulated.

• 대한교통학회지
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• 제27권6호
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• pp.157-166
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• 2009

교통망설계문제(network design problem, NDP)는 교통체계(transportation system)을 최적화시키는 설계변수(design parameter, design variable)를 구하는 문제이다. 본 연구에서는 교통망설계문제를 조금 변환시킨 목표지향 교통망설계문제(target-oriented network design problem, target-oriented NDP)를 제시하고 이를 풀기 위한 기법도 제시한다. 목표지향 교통망설계는 교통운영자(traffic operator) 또는 관리자(travel manager)가 특정 교통정책 목표(target)를 미리 설정하고 이를 달성하기 위한 최적 설계변수를 찾는 문제이다. 즉, 일반적인 교통망설계문제(general NDP)는 총통행비용이나 순편익 등 특정목적함수를 최적화시키는 설계변수를 찾는데 반해, 목표지향 교통망설계(target NDP)는 사전에 설정된 목표수준(target level)을 달성하기 위한 설계변수를 구하는 문제이다. 본 연구에서 제시된 목표지향 교통망설계모형을 교통수단분담문제에 적용하여 모형을 평가한다.

• 대한산업공학회지
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• 제29권2호
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• pp.179-189
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• 2003

Gate poly-silicon critical dimension is a prime characteristic of a metal-oxide-semiconductor field effect transistor. It is important to achieve the uniformity of gate poly-silicon critical dimension in order that a semiconductor device has acceptable electrical test characteristics as well as a semiconductor wafer fabrication process has a competitive net-die-per-wafer yield. However, on gate poly-silicon critical dimension, the complexity associated with a semiconductor wafer fabrication process entails hierarchical variance components according to run-to-run, wafer-to-wafer and even die-to-die production unit changes. Specifically, estimates of the hierarchical variance components are required not only for disclosing dominant sources of the variation but also for testing the wafer-level uniformity. In this paper, two experimental designs, a two-stage nested design and a randomized complete block design are considered in order to estimate the hierarchical variance components. Since gate poly-silicon critical dimensions are collected from fixed die positions within wafers, a factor representing die positions can be regarded as fixed in linear statistical models for the designs. In this context, the two-stage nested design also checks the wafer-level uniformity taking all sampled runs into account. In more detail, using variance estimates derived from randomized complete block designs, Duncan's multiple range test examines the wafer-level uniformity for each run. Consequently, a framework presented in this study could provide guidelines to practitioners on estimating the hierarchical variance components and testing the wafer-level uniformity in parallel for any characteristics concerned in semiconductor wafer fabrication processes. Statistical analysis is illustrated for an experimental dataset from a real pilot semiconductor wafer fabrication process.

• 설비공학논문집
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• 제21권8호
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• pp.468-474
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• 2009

Ground water source heat pump system is the oldest one of the ground source heat pump systems. Despite of this, little formal design information has been available until recently. The important design parameters for open system are the identification of optimum ground water flow, heat exchanger selection and well pump. In this study, the capacity of 50 RT system of two well type ground water heat pump system was used. As a result, static water level was -7 m and the level during the heating operation was -32 m, cooling operation was -40 m. The initial static water level recovered within 48 hrs. The temperature of ground water is $15.6^{\circ}C$ for heating season and $16.2^{\circ}C$ for cooling season and does not depend on the outdoor temperature. Operation efficiency of the system shows that, COP 3.1 for heating and COP 4.2 for cooling.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제12권12호
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• pp.6079-6097
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• 2018

Safety-related systems (SRSs) has widely used in shipbuilding and power generation to prevent fatal accidents and to protect life and property. Thus, SRS performance is a high priority. The safety integrity level (SIL) is the relative performance level of an SRS with regard to its ability to operate reliably in a safe manner. In this article, we proposed an optimal design procedure to achieve the targeted SIL of SRSs. In addition, a more efficient failure mode and effects diagnostic analysis (FMEDA) process and optimization model were developed to improve cost efficiency. Based on previous IEC 61508 diagnostic analyses that revealed unnecessary costs associated with excessive reliability, the new approach consists of two phases: (i) SIL evaluation by FMEDA, and (ii) solution optimization for achieving the target SIL with minimal cost using integer-programming models. The proposed procedure meets the required safety level and minimizes system costs. A case study involving a gas-detection SRS was conducted to demonstrate the effectiveness of the new procedure.

• 한국시뮬레이션학회논문지
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• 제3권1호
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• pp.107-114
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• 1994

This paper describes an integrated environment for logic circuit simultion which is an important step of logic circuit design. The system consists of a logic simulator kernel, an expandible element routine library. a functional level element routine generator, several HDL input parsers, and a postprocessor. The system can simulate the same system in several levels of hierarchy. The experimental result shows that the system is very efficient and useful for design of logic circuits.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 G
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• pp.3233-3235
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• 1999

This paper describes development of a microprocessor-based optoelectronic guard system established a higher level of control reliability in machine guard design. The system uses the design concept of diverse redundancy and a fast software algorithm. We have accomplished an safety light curtain system that allows to be intentionally disabled moving machine by the interrupt of dangerous situations. As a result, it is showed that the proposed system is effective enough to practical applications.

• 마이크로전자및패키징학회지
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• 제29권1호
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• pp.1-6
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• 2022

The mobile device industry demands much higher levels of integration and lower costs coupled with a growing awareness of the complete system's configuration. A subsystem module package is similar to a board-level circuit that integrates a system function in a package beyond a System-in-Package (SiP) design. It is an advanced IC packaging solution to enhance the PDN and achieve a smaller form factor. Unlike a system-level design with a decoupling capacitor, a subsystem module package system needs to redefine the role of the capacitor and its configuration for PDN performance. Specifically, the design of package's form factor should include careful consideration of optimal PDN performance and the number of components, which need to define the decoupling capacitor's value and the placement strategy for a low impedance profile with associated cost benefits. This paper will focus on both the static case that addresses the voltage (IR) drop and AC analysis in the frequency domain with three specific topics. First, it will highlight the role of simulation in the subsystem module design for the PDN. Second, it will compare the performance of double-sided component placement (DSCP) motherboards with the subsystem module package and then prove the advantage of the subsystem module package. Finally, it will introduce three-terminal decoupling capacitor (decap) configurations of capacitor size, count and value for the subsystem module package to determine the optimum performance and package density based on the cost-effective model.