• Transactions of the Korean Society of Automotive Engineers
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• v.18 no.5
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• pp.56-61
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• 2010

This paper presents dynamic clearance verification considering engine movement for vehicle engine room package and validates through physical vehicle test. Traditionally, static clearance guide has been used for engine room package, but it's only 2-dimension criteria that results in requiring unnecessary space and it's not possible to conduct engine movement with real driving conditions. Thus, the dynamic DMU considers engine movement based on 28 load cases that are Roll Data analyzed by CAE for maximum engine movement and visualizes part-to-part dynamic clearance into virtual space. The dynamic DMU enables to develop compact engine room package without unnecessary space. The result of comparison between simulation and physical test has 0.892 correlation coefficient.

• Journal of electromagnetic engineering and science
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• v.11 no.1
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• pp.62-69
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• 2011

This paper proposes a novel electrical characterization approach for a high-performance package system using an improved Partial Element Equivalent Circuit (PEEC). As the effect of interconnects becomes a pivotal factor for the performance of high-speed electronic systems, there is a great demand for an accurate equivalent model for interconnects. In particular, an equivalent model of interconnects is established in this paper for the Fine-Pitch Ball Grid Array (FBGA) package using the improved PEEC method. Based on the equivalent model, electrical characteristics are analyzed; furthermore, these are verified through the measurement results of a Vector Network Analyzer (VNA).

• Journal of Applied Reliability
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• v.10 no.2
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• pp.137-148
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• 2010

This study deals with the accelerated life test of high power phosphor converted white Light Emitting Diodes (High power LEDs). Samples were aged at $110^{\circ}C$/85% RH and $130^{\circ}C$/85% RH up to 900 hours under non-biased condition. The stress induced a luminous flux decay on LEDs in all the conditions. Aged devices exhibited modification of package silicon color from white to yellowish brown. The instability of the package contributes to the overall degradation of optical lens and structural degradations such as generating bubbles. The degradation mechanisms of lumen decay and reduction of spectrum intensity were ascribed to hygro-mechanical stress which results in package instabilities.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.153-154
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• 2008

This paper presents a window-based software package for the education and training for the reduction of power system by using locational marginal price (LMP), clustering, and similarity indices of each bus. The developed package consists of three modules: 1) the LMP module, 2) the Clustering module and 3) the Reduction module. Each module has a separated and interactive interface window. First of all, LMPs are created in the LMP module, and then the Clustering module carries out clustering based on the results of the LMP module. Finally, groups created in this Clustering module are reduced by using the similarity indices of each bus. The developed package displays a variety of tables for results of the LMPs of base network, voltages, phases and power flow of reduced network so that the user can easily understand the reduction of network. To demonstrate the performance of the developed package, it is tested for the IEEE 39-bus power system.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.3
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• pp.75-80
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• 2013

According to advance of electronic packaging technology, electronic package becomes smaller. Miniaturization of package causes the temperature rise of package. This can degrade life of electronic device and generate the failure of electronic system. In this study, we proposed a new semi-embedded structure with micro pattern for maximizing heat dissipation. A proposed structure showed the characteristics which have maximum temperature lower than $20^{\circ}C$ compared with conventional structure. And also, in view of thermal stress and strain, our structure showed a remarkably low value compared with other ones. We expect that the new structure proposed in this work can be applied to an flip-chip package of the future.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2003.05a
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• pp.34-39
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• 2003

Seam seal welding on the semi-conductor package is a process for sealing the packages of semiconductors, crystal parts, saw filters, oscillators with lid plate by seam welding. This paper present the development process of automatic seam seal welding system. In this process, the process algorithm, high precision welding current control, design of welding head, high speed and high precision feeding mechanism, user interface process control program technologies are included.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.1
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• pp.684-692
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• 2016

In the manufacturing process of the LQFP/TQFP (Low-profile Quad Flat Package/Thin Quad Flat Package), the requirement of a 3 dimensional inspection is increasing rapidly and a 3D inspection of the shape of a chip has become an important report of quality control. This study developed a 3 dimensional measurement system based on PMP (Phase Measuring Profilometry) for an inspection of the LQFP/TQFP chip and image processing algorithms. The defects of the LQFP/TQFP chip were classified according to the dimensions. The 2 dimensional optical system was designed by the dorm illumination to achieve constant light distribution, In the 3 dimensional optical system, PZT was used for moving 90 degree in phase. The problem of 2 ambiguity was solved from the measured moir? pattern using the ambiguity elimination algorithm that finds the point of ambiguity and refines the phase value. The proposed 3D measurement system was evaluated experimentally.

• Proceedings of the KIEE Conference
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• 2001.11c
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• pp.450-452
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• 2001

In this paper, we proposed the automatic postal drop-off system based on the microprocessor board or PC. The weight of the small postal package is transmitted from the electronic scale and user-entered addresses and delivery rate are processed by the controller to calculate the fee. For 24 hour out-door operation and maintenance, non-cash payment methods such as credit card payment is used. The post stamp and receipt are printed by the thermal printer. For the electronic processing of the parcel, serial code is also printed on the stamp and receipts in bar code format. The parcel information obtained by the automatic postal drop-off system is transferred to remote central system by dial-up modem shared by the on site office. The proposed system and its control software are built for prototype model operation and the result met the design requirements. For real time processing, data reception through three serial ports is handled by interrupt routine. The proposed system is expected to be applied for commercial logistics system and pc automation system.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.09a
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• pp.219-225
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• 2002

This paper presents a novel "bumpless flip chip package"for cost! performance driven devices. Using the conventional electroplating and etching processes, this package enables the production of fine pitch BGA up to 256 I/O with single layer routing. An array of circuitry down to $25-50{\mu}{\textrm}{m}$ line/space is fabricated to fan-in and fan-out of the bond pads without using bumps or substrate. Various types of joint methods can be applied to connect the fine trace and the bond pad directly. The resin-filled terminal provides excellent compliancy between package and the assembled board. More interestingly, the thin film routing is similar to wafer level packaging whereas the fan-out feature enables high lead count devices to be accommodated in the BGA format. Details of the design concepts and processing technology for this novel package are discussed. Trade offs to meet various cost or performance goals for selected applications are suggested. Finally, the importance of design integration early in the technology development cycle with die-level and system-level design teams is highlighted as critical to an optimal design for performance and cost.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.189-195
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• 2004

A 10 Gb/s limiting amplifier IC with the emitter area of $1.5{\times}10{\mu}m^2$ for optical transmission system was designed and fabricated with a AIGaAs/GaAs HBTs technology. In this stud)', we evaluated fine pitch bump using WL-CSP (Wafer Level-Chip Scale Packaging) instead of conventional wire bonding for interconnection. For this we developed WL-CSP process and formed fine pitch solder bump with the $40{\mu}m$ diameter and $100{\mu}m$ pitch on bonding pad. To study the effect of WL-CSP, electrical performance was measured and analyzed in wafer and package module using WL-CSP. In a package module, clear and wide eye diagram openings were observed and the riselfall times were about 100ps, and the output" oltage swing was limited to $600mV_{p-p}$ with input voltage ranging from 50 to 500m V. The Small signal gains in wafer and package module were 15.56dB and 14.99dB respectively. It was found that the difference of small signal gain in wafer and package module was less then 0.57dB up to 10GHz and the characteristics of return loss was improved by 5dB in package module. This is due to the short interconnection length by WL-CSP. So, WL-CSP process can be used for millimeter wave GaAs MMIC with the fine pitch pad.