• Journal of IKEEE
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• v.19 no.2
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• pp.176-185
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• 2015

The study aims to a design hybrid frequency synthesizer in spectrum analyzer and to propose new techniques designed for evasion of in-band spurious. The study focuses on calculating the exact location of multiple phase locked loop of hybrid frequency synthesizer and spurious of direct digital synthesizer to evade in-band spurious outside of frequency range that the user wants to see and thereby simulating technique to improve input related spurious of spectrum analyzer for algorithm. The proposed technique is designed to calculate spurious evasion algorithm in central processing system when in-band spurious arises, and to move output frequency of DDS(direct digital synthesizer) into the place where no in-band spurious exists thereby improving performance of frequency synthesizer. The study used simulation and result representation to prove the effectiveness of the proposed technique.

• Journal of the Korea Institute of Military Science and Technology
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• v.20 no.5
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• pp.673-680
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• 2017

In the proposed paper, we designed low noise frequency synthesizer with compact size for Multi-Band. The proposed frequency synthesizer consists of fundamental frequency band(2 GHz) and harmonic frequency band(4 GHz). To improve the phase noise and spurious level of frequency synthesizer, we analyze how the configuration of frequency synthesizer affect the phase noise and design the multi-band's structure. The implemented frequency synthesizer reduce both the phase noise and spurious level. The phase noise is -92.17 dBc/Hz at 1 kHz frequency offset in 2 GHz and -90.50 dBc/Hz at 1 kHz frequency offset in 4 GHz. All spurious signals including fundamental frequency are suppressed at least 20 dBc than the second harmonic frequency.

• Journal of Satellite, Information and Communications
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• v.6 no.1
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• pp.45-49
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• 2011

In this paper, we present the high resolution and low phase noise frequency synthesizer for satellite terminal. To improve the phase noise of frequency synthesizer, we analyze how the configuration of frequency synthesizer affect the phase noise. The implemented frequency synthesizer reduce the phase noise and show the high resolution. The output power of this frequency synthesizer is over -2dBm in 950~1450MHz and the phase noise of the -101dBc/Hz at 10kHz frequency offset.

• Journal of the Korea Institute of Military Science and Technology
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• v.17 no.5
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• pp.629-636
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• 2014

In the proposed paper, we designed low phase noise frequency synthesizer for Ku-band. The proposed up-mixing frequency synthesizer consists of narrow local oscillation part and variable frequency oscillation part. To improve the phase noise of frequency synthesizer, we analyze how the configuration of frequency synthesizer affect the phase noise. The implemented frequency synthesizer reduce the phase noise. The phase noise is -95.18dBc/Hz at 7kHz frequency offset in 16GHz and -94.27dBc/Hz at 7kHz frequency offset in 16.125GHz.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.978-981
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• 1999

In this paper, an improved integer-N frequency synthesizer that can be synthesized into smaller channel space than input signal frequency is presented. The proposed frequency synthesizer also has an characteristics of fast phase locking time. The frequency synthesizer performed in the manner that it divides various outputs of different phases in VCO by means of dividers that have different control signals respectively and then add the divided signal. In order to confirm the characteristics of proposed frequency synthesizer, behavioral and SPICE simulations are performed using C-language and HSPICE respectively.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.1
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• pp.19-25
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• 2001

In this paper, the design and simulation results of IF frequency synthesizer section has been described. We has been used 0.8 $\mu\textrm{m}$ BiCMOS device and library of the AMS. IF frequency synthesizer section has been contained IF VCO, Phase Detector, Divide_by_8, Charge Pump and Loop Filter. IF frequency synthesizer has been shown operating voltage of 2.7~3.6 V, control voltage of 0.5~2.7 V and supply current of 11 mA. The measured results have been showed good agreement with the simulation results about supply current.

• ETRI Journal
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• v.29 no.4
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• pp.437-444
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• 2007

A CMOS frequency synthesizer block for multi-band orthogonal frequency division multiplexing ultra-wideband systems is proposed. The proposed frequency synthesizer adopts a double-conversion architecture for simplicity and to mitigate spur suppression requirements for out-of-band interferers in 2.4 and 5 GHz bands. Moreover, the frequency synthesizer can consist of the fewest nonlinear components, such as divide-by-Ns and a mixer with the proposed frequency plan, leading to the generation of less spurs. To evaluate the feasibility of the proposed idea, the frequency synthesizer block is implemented in 0.18-${\mu}m$ CMOS technology. The measured sideband suppression ratio is about 32 dBc, and the phase noise is -105 dBc/Hz at an offset of 1 MHz. The fabricated chip consumes 17.6 mA from a 1.8 V supply, and the die-area including pads is $0.9{\times}1.1\;mm^2$.

• Journal of the Korea Institute of Military Science and Technology
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• v.15 no.4
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• pp.450-457
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• 2012

In this paper, we designed low phase noise frequency synthesizer with compact size for High frequency band (Ku-band). The paper addresses merits and demerits of single loop and dual loop frequency synthesizer. The phase noise characteristics of the phase-locked loop frequency synthesizer were predicted based on the analysis for phase noise contribution of noise sources. The proposed model in this paper more accurately predicts the low phase noise frequency synthesizer with compact size for high frequency band.

• International journal of advanced smart convergence
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• v.11 no.2
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• pp.53-58
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• 2022

In this paper, w-band frequency synthesizer was developed for frequency-modulated continuous wave (FMCW) radar sensors. To achieve a small size and high performance, We designed and manufactured w-band MMIC chips such as up-converter one-chip, multiplier, DA (Drive Amplifier) MMIC(Monolithic Microwave Integrated Circuit), etc. And interposer technology was applied between the W-band multiplier and the DA MMIC chip. As a result, the measured phase noise was -106.10 dBc@1MHz offset, and the frequency switching time of the frequency synthesizer was less than 0.1 usec. Compared with the w-band frequency synthesizer using purchased chips, the developed frequency synthesizer showed better performance.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.2
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• pp.258-264
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• 2011

In this paper, we designed a frequency synthesizer with a low phase noise and fast lock time and excellent spurious characteristics using the offset-PLL(Phase Locked Loop) that is used in GSM(Global System for Mobile communications). The proposed frequency synthesizer has low phase noise using three times down conversion and third offset frequency of this synthesizer is created by DDS(Direct Digital Synthesizer) to have high frequency resolution. Also, this synthesizer has fast switching speed using DAC(Digital to Analog Converter). but phase noise degraded due to DAC. we improved performance using the DAC noise filter.