• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.329-332
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• 2000

This paper proposed resource allocation algorithm for the minimum power consumption of functional unit in high level synthesis process as like DSP which is circuit to give many functional unit. In this paper, the proposed method though high level simulation find switching activity in circuit each functional unit exchange for binary sequence length and value bit are logic one value. To used the switching activity find the allocation with minimal power consumption, the proposed method visits all control steps one by one and determines the allocation with minimal power consumption at each control step.

• Proceedings of the Korean Magnestics Society Conference
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• 2002.12a
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• pp.186-187
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• 2002

Recently, there has been much interest in magnetic thin film patterned in submicron scale because of possible ultrahigh density storage media or logical device applications [1-3]. Various geometries such as rectangle, circle, ring and ellipse type dots have been studied to find the shape showing stable switching behavior from repeated cycles. However, rectangle and circle types may not be suitable for device applications because they have two uncontrollable different magnetization reversal modes: C state and S state, resulting in different coercivity and irreproducible switching[4]. (omitted)

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.3
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• pp.41-46
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• 1992

In this paper we report how to design integrated-mirror etalons for surface-emitting lasers and photonic switching without time-consuming numerical calculation. It consists of the following two-step process (step 1) find the minimum reflectance to achieve the maximum allowable linewidth. (step 2) find the number of the quarter-wave layers in each mirror to realize the reflectance given by step 1. The condition for maximum transmission in an integrated- mirror etalon is also derived. Under this condition we can achieve the required linewidth with the minimum number of quarterwave layers.

• Proceedings of the Korean Magnestics Society Conference
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• 2005.12a
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• pp.216-216
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• 2005

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.9
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• pp.26-37
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• 2016

The core technologies of the current transport network are OAM and protection switching to meet the sub-50ms protection switching time via a path redundancy when a link or node failure occurs. The transport networks owned by public network operators, central/local governments, and major enterprises are individually configured and managed with service resiliency in each own protected sub-network. When such networks are cascaded, it is also important to provide a node resiliency between two protected sub-networks. However, the linear protection switching in packet transport networks, such as MPLS-TP and Carrier Ethernet, does not define a solution of dual node interconnection. Although Ethernet ring protection switching covers the dual node interconnection scheme, a large amount of duplicated data frames may be flooded when a failure occurs on an adjacent (sub) ring. In this paper, we suggest a dual node interconnection scheme with linear protection switching technology in multiple protected sub-networks. And we investigate how various protected sub-network combinations with a proposed linear or ring protection process impact the service resiliency of multiple protected sub-networks through extensive experiments on link and interconnected node failures.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.5A
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• pp.889-901
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• 2001

본 논문에서 Multiprotocol Label Switching 시스템을 위한 Label Distribution Protocol의 개발과 분석에 관해서 기술한다. 먼저 Gigabit Switched Router를 만들기 위해서, 상용화시 Carrier Class 제품에 적용하기 위한 LDP의 구현시 고려해야 될 사항에 대해 살피고, 상세 설계를 제안한다. IETF 표준에 의거한 LDP의 구현을 위한 상세 설계는 프로토콜 상태기계의 유도 트리와 프로세스 대수를 사용한 형식적 명세를 사용하여 제시한다. 본 논문에서는 제시된 유도트리와 프로세스 대수를 사용한 프로토콜 동작의 분석을 통해, 구현된 LDP의 상호 연동성과 완전성, 생존성, 도달성, 안전성을 검증한다. 또한 이를 사용하여 구현된 LDP가 기존 상용 제품들과의 연동성과 그 동작의 신뢰성을 확보할 것을 기대한다. 결과적으로 구현된 LDP의 프로토콜 동작들의 검증을 제공한다.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.439-442
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• 2004

Timing delays due to VLSI circuit interconnects strongly depend on neighbor line switching patterns as well as input transition time. Considering both the input transition and input switching pattern, a new analytical timing delay model is developed by using the decoupling technique of transfer multi-coupled lines into an effective single line. The analytical timing delay model can determine the timing delay of multi-coupled lines accurately as well as rapidly. It is verified by using DSM-Technology ($0.1{\mu}m$ /low-k copper-based process) that the model has excellent agreement with the results of SPICE simulation.

• Proceedings of the KIPE Conference
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• 2016.07a
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• pp.40-41
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• 2016

The inverter resistance welder requires AC/DC converter of high efficiency because the converter changes a commercial ac power source to low voltage dc power source. Harmonic components that occur in the conversion process of converter decrease system power factor and deal great damage in electric power system. To improve such problems, this paper proposes a high efficiency AC/DC converter for inverter resistance welder. The switching devices in the proposed converter are operated by soft switching technique using a new quasi-resonant circuit. As a result, the proposed AC/DC converter obtains low switching power loss and high efficiency.

• Proceedings of the Safety Management and Science Conference
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• 2001.05a
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• pp.189-193
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• 2001

This paper analyses the tool switching problem in the dynamic environment, where parts to be processed on a flexible machine arrive randomly. As the total number of tools required to Process a set of parts on the machine is generally larger than the available magazine storage capacity, tool switches between parts are usually necessary. We assume that tool switching must be made just before the processing of the parts. Since the time required for tool switches can be significant relative to processing time and cause the processing of parts to be delayed, it is desirable to minimize the number of tool switches. Therefore, we present one heuristic algorithm to minimize the total number of tool switches and the t)reposed heuristic is compared with the KTNS (Keep Tool Needed Soonest) policy on randomly generated problems.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.26 no.11
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• pp.62-74
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• 2012

This paper proposes a new secondary battery charger/discharger available for zero voltage discharge which is used for test equipments and formation process. The proposed system is a switching type converter, and thus the system is high efficiency and more compact as compared with linear type charger/discharger. Conventional switching type charger/discharger can not discharge secondary batteries to zero voltage because of voltage drops in the switching elements and long distributing line(typically 10m). However, the proposed system is able to discharge the battery to zero voltage in constant current mode regardless of the voltage drops. In this paper, we analyze the proposed charger/discharger and the validity of the system is verified by simulation and experiment.