• Journal of Power Electronics
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• v.16 no.5
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• pp.1689-1697
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• 2016

Continuous conduction mode (CCM) boost converters are commonly used in home appliances and various industries because of their simple topology and low input current ripples. However, these converters suffer from several disadvantages, such as hard switching of the active switch and reverse recovery problems of the output diode. These disadvantages increase voltage stresses across the switch and output diode and thus contribute to switching losses and electromagnetic interference. A new topology is presented in this work to improve the switching characteristics of CCM boost converters. Zero-current turn-on and zero-voltage turn-off are achieved for the active switches. The reverse-recovery current is reduced by soft turning-off the output diode. In addition, an input current sensorless control is applied to the proposed topology by pre-calculating the duty cycles of the active switches. Power factor correction is thus achieved with less effort than that required in the traditional method. Simulation and experimental results verify the soft-switching characteristics of the proposed topology and the effectiveness of the proposed input current sensorless control.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.05a
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• pp.141-148
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• 2002

In a motor driving, the current rate is directly related to the rate of a switching device and in cost reduction, the parallel switching operation is the alternatives because it has the smaller current rate through current division. There are many investigations for the parallel switching operations to equaling the current division. However it remains many problems for practical usage. The reason is that the switching characteristics are mainly relied on the different saturation voltage of each device etc. and these factors are not altered by circuit designer. In order to compensate this problem, a proper resistance is experimently inserted to the switching device. But this method can not be the optimal solution. Therefore this paper proposes a new parallel operation which uses a parallel phase winding to remove the traditional effect of switching device such as saturation voltage according to the division of current. Also the reliable and stable driving is improved through experiments and the detailed principles.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.37-40
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• 2000

Multi Protocol Label Switching (MPLS) is a high performance method for forwarding packets (frames) through a network. It enables routers at the edge of a network to apply simple labels to packets (frames). we use MPLS in the core network for internet. MPLS provide high speed switching and traffic engineering in MPLS domain but at the Label Edge Router(LER) there is frequently cell discarding via congestion and buffer management method. It is one of the most important reasons retransmission and congestion. In this paper we propose advanced LER scheme that provide less cell loss rate also efficient network infrastructure.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.329-332
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• 2000

This paper proposed resource allocation algorithm for the minimum power consumption of functional unit in high level synthesis process as like DSP which is circuit to give many functional unit. In this paper, the proposed method though high level simulation find switching activity in circuit each functional unit exchange for binary sequence length and value bit are logic one value. To used the switching activity find the allocation with minimal power consumption, the proposed method visits all control steps one by one and determines the allocation with minimal power consumption at each control step.

• 제어로봇시스템학회:학술대회논문집
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• 1986.10a
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• pp.576-579
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• 1986

In this paper, a design method of an optimal output PIM(Proportional-Integral-Measurable) controller is presented so that the closed-loop output response of the switching regulator closely match to that of ideal model system satisfying the time domain specifications. The computer simulation for a design example is given to show the usefulness of the proposed technique.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.345-348
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• 2001

In this paper, we present a effective low-power technique which can reduce significantly the switching activity in instruction address bus, pipeline and I-cache. Using this method, named Guarded Operation, we has implemented address register. address bus architecture without complex hardware and designed loop buffer without tag. These architectures reduce 67% of switching activity with little overhead and also increase instruction-fetch performance.

• Proceedings of the IEEK Conference
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• 2000.06e
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• pp.13-16
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• 2000

This paper presents a simple class-D stereo amplifier using 3-phase full bridge circuit configurations which is controlled by a new current control switching method. Although this class-D amplifier has an only one current control loop with the proposed switching method, a good performance can be obtained. In this paper, a strategy for driving stereo signal amplifier with 3-phase full bridge is discussed. With the experimental results, usefulness of the proposed amplifier is confirmed.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.8
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• pp.45-55
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• 1997

To design a ATM Switch which ahs advantages in high sped packet switching, it is essential to set multiple paths between input ports and output ports and to design a new packet transfer technique on that paths for decreasing Packet Loss by conflicts in internal Switch Plane. We propose new packet transfer method, Alternate Path Transfer Mechanism by Dynamic Bypass Transfer Method which can solve conflict problem in Banyan network easily. Proposed ATM Switch consists of Banyan networks, Input/Ouput Port, Bypass Link, and Bypass Link Controller. Packets caused conflicts in SEs have another chances of packet transfer over alternate switching planes by using this mechanism.

• Journal of information and communication convergence engineering
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• v.8 no.4
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• pp.421-426
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• 2010

This paper presents a method of design the counter using sequential system based on synchronous techniques. For the design the counter, first of all, we derive switching algebras and their operations. Also, we obtain the next-state functions, flip-flop excitations and their input functions from the flip-flop. Then, we propose the algorithm which is a method of implementation of the synchronous sequential digital logic circuits. Finally, we apply proposed the sequential logic based on synchronous techniques to counter.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.1084-1087
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• 2000

This paper presents a new approach to evaluate the maximum number of simultaneous switching gates of a given combinational circuit. The new approach is based on an iterative method proposed by Sinogi et al. and applies a simulated annealing strategy to search jot a new solution. The experimental evaluation using ISCAS’85 benchmark circuits shows that the proposed approach has attained an excellent improvement compared with other rotated methods including the iterative method.