Instruction addressing method and implemetation for low pouter system by using guarded operation

Guarded Operation을 이용한 명령어 어드레싱 방법 및 구현

In this paper, we present a effective low-power technique which can reduce significantly the switching activity in instruction address bus, pipeline and I-cache. Using this method, named Guarded Operation, we has implemented address register. address bus architecture without complex hardware and designed loop buffer without tag. These architectures reduce 67% of switching activity with little overhead and also increase instruction-fetch performance.