• ETRI Journal
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• v.45 no.4
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• pp.615-626
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• 2023

Under limited transmission conditions, many factors affect the efficiency of video transmission. During the flight of an unmanned aerial vehicle (UAV), frequent network switching often occurs, and the channel transmission condition changes rapidly, resulting in low-video transmission efficiency. This paper presents an efficient video coding flow for UAVs working in the 5G nonstandalone network and proposes two bit controllers, including time and spatial bit controllers, in the flow. When the environment fluctuates significantly, the time bit controller adjusts the depth of the recursive codec to reduce the error propagation caused by excessive network inference. The spatial bit controller combines the spatial bit mask with the channel quality multiplier to adjust the bit allocation in space to allocate resources better and improve the efficiency of information carrying. In the spatial bit controller, a flexible mini graph is proposed to compute the channel quality multiplier. In this study, two bit controllers with end-to-end codec were combined, thereby constructing an efficient video coding flow. Many experiments have been performed in various environments. Concerning the multi-scale structural similarity index and peak signal-to-noise ratio, the performance of the coding flow is close to that of H.265 in the low bits per pixel area. With an increase in bits per pixel, the saturation bottleneck of the coding flow is at the same level as that of H.264.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.6
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• pp.715-720
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• 2016

This paper proposes a PWM (Pulse Width Modulation) voltage mode DC-DC step-up converter for portable devices. The converter, which is operated with a 1 MHz switching frequency, is capable of reducing the mounting area of passive devices, such as inductor and capacitor, and is suitable for compact mobile products. This step-up converter consists of a power stage and a control block. The circuit elements of the power stage are an inductor, output capacitor, MOS transistors Meanwhile, control block consist of OPAMP (operational amplifier), BGR (band gap reference), soft-start, hysteresis comparator, and non-overlap driver and some protection circuits (OVP, TSD, UVLO). The hysteresis comparator and non-overlapping drivers reduce the output ripple and the effects of noise to improve safety. The proposed step-up converter was designed and verified in Magnachip/Hynix 0.18um 1-poly, 6-metal CMOS process technology. The output voltage was 5 V with a 3.3 V input voltage, output current of 100 mA, output ripple less than 1% of the output voltage, and a switching frequency of 1 MHz. These designed DC-DC step-up converters could be applied to the Personal Digital Assistants(PDA), cellular Phones, Laptop Computer, etc.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.12
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• pp.3235-3245
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• 1996

A DDFS(Direct Digital Frequency Synthesizer) used in spread spectrum communication systems must need fast switching speed, high resolution(the step size of the synthesizer), small size and low power. The chip has been designed with four parallel sine look-up table to achieve four times throughput of a single DDFS. To achieve a high processing speed DDFS chip, a 24-bit pipelined CMOS technique has been applied to the phase accumulator design. To reduce the size of the ROM, each sine ROM of the DDFS is stored 0-.pi./2 sine wave data by taking advantage of the fact that only one quadrant of the sine needs to be stored, since the sine the sine has symmetric property. And the 8 bit of phase accumulator's output are used as ROM addresses, and the 2 MSBs control the quadrants to synthesis the sine wave. To compensate the spectrum purity ty phase truncation, the DDFS use a noise shaper that structure like a phase accumlator. The system input clock is divided clock, 1/2*clock, and 1/4*clock. and the system use a low frequency(1/4*clock) except MUX block, so reduce the power consumption. A 107MHz DDFS(Direct Digital Frequency Synthesizer) implemented using 0.8.mu.m CMOS gate array technologies is presented. The synthesizer covers a bandwidth from DC to 26.5MHz in steps of 1.48Hz with a switching speed of 0.5.mu.s and a turing latency of 55 clock cycles. The DDFS synthesizes 10 bit sine waveforms with a spectral purity of -65dBc. Power consumption is 276.5mW at 40MHz and 5V.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.7 no.6
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• pp.63-69
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• 2008

Reconfigurable RF one-chip solutions have been researched with the objective of designing for smaller-sized and more economical RF transceiver and it can be applied to a vehicular wireless terminal. The proposed voltage-controlled oscillator satisfies the targeted frequency range ($4.2{\sim}5.4\;GHz$) and the frequency planning which correspond to the standards such as CDMA(IS-95), PCS, GSM850, EGSM, WCDMA, WLAN, Bluetooth, WiBro, S-DMB, DSRC, GPS, and DVB-H/DMB-H/L(L Band). In order to improve phase noise performance, PMOS is adopted in the cross-coupled pair, the tail current source and MOS varactor in this VCO and differential-typed switching is proposed in capacitor array. Based on the measurement results, a total power dissipation is $5.3{\sim}6.0\;mW$ at 1.8 V power supply voltage. The oscillator is tuned from 4.05 to 5.62 GHz; The tuning range is 33%. The phase noise is -117.16 dBc/Hz at 1 MHz offset frequency and the FOM (Figure Of Merit) is $-180.84{\sim}-180.5$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.27-35
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• 2008

This work proposes a 14b 150MS/s 0.13um CMOS ADC for SDR systems requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC employs a calibration-free four-step pipeline architecture optimizing the scaling factor for the input trans-conductance of amplifiers and the sampling capacitance in each stage to minimize thermal noise effects and power consumption at the target resolution and sampling rate. A signal- insensitive 3-D fully symmetric layout achieves a 14b level resolution by reducing a capacitor mismatch of three MDACs. The proposed supply- and temperature- insensitive current and voltage references with on-chip RC filters minimizing the effect of switching noise are implemented with off-chip C filters. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates a measured DNL and INL within 0.81LSB and 2.83LSB, at 14b, respectively. The ADC shows a maximum SNDR of 64dB and 61dB and a maximum SFDR of 71dB and 70dB at 120MS/s and 150MS/s, respectively. The ADC with an active die area of $2.0mm^2$ consumes 140mW at 150MS/s and 1.2V.

• Journal of Biomedical Engineering Research
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• v.25 no.4
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• pp.269-275
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• 2004

Different biological tissues have different values of electrical resistivity. In EIT (electrical impedance tomography), we try to provide cross-sectional images of a resistivity distribution inside an electrically conducting subject such as the human body mainly for functional imaging. However, it is well known that the image reconstruction problem in EIT is ill-posed and the quality of a reconstructed image highly depends on the measurement error. This requires us to develop a high-performance EIT system. In this paper, we describe the development of a 16-channel digital EIT system including a single constant current source, 16 voltmeters, main controller, and PC. The system was designed and implemented using the FPGA-based digital technology. The current source injects 50KHz sinusoidal current with the THD (total harmonic distortion) of 0.0029% and amplitude stability of 0.022%. The single current source and switching circuit reduce the measurement error associated with imperfect matching of multiple current sources at the expense of a reduced data acquisition time. The digital voltmeter measuring the induced boundary voltage consists of a differential amplifier, ADC, and FPGA (field programmable gate array). The digital phase-sensitive demodulation technique was implemented in the voltmeter to maximize the SNR (signal-to-noise ratio). Experimental results of 16-channel digital voltmeters showed the SNR of 90dB. We used the developed EIT system to reconstruct resistivity images of a saline phantom containing banana objects. Based on the results, we suggest future improvements for a 64-channel muff-frequency EIT system for three-dimensional dynamic imaging of bio-impedance distributions inside the human body.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.1
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• pp.47-56
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• 1999

As the density of logic gates of VLSI chips has rapidly increased, more number of I/O pins has been required. This results in bigger package size and higher packager cost. The package cost is higher than the cost of bare chips for high I/O count VLSI chips. As the density of logic gates increases, the reduction method of the number of I/O pins for a given complexity of logic gates is required. In this paper, we propose the novel I/O interface circuit using CTR (Constant-Transition-Rate) code to reduce 50% of the number of I/O pins. The rising and falling edges of the symbol pulse of CTR codes contain 2-bit digital data, respectively. Since each symbol of the proposed CTR codes contains 4-bit digital data, the symbol rate can be reduced by the factor of 2 compared with the conventional I/O interface circuit. Also, the simultaneous switching noise(SSN) can be reduced because the transition rate is constant and the transition point of the symbols is widely distributed. The channel encoder is implemented only logic circuits and the circuit of the channel decoder is designed using the over-sampling method. The proper operation of the designed I/O interface circuit was verified using. HSPICE simulation with 0.6 m CMOS SPICE parameters. The simulation results indicate that the data transmission rate of the proposed circuit using 0.6 m CMOS technology is more than 200 Mbps/pin. We implemented the proposed circuit using Altera's FPGA and confimed the operation with the data transfer rate of 22.5 Mbps/pin.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.60-67
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• 2008

A low-power 2.4GHz fractional-N frequency synthesizer has been designed for 2.4GHz ISM band applications such as Bluetooth, Zigbee, and WLAN. To achieve low-power characteristic, the design has been focused on the power optimization of power-hungry blocks such as VCO, prescaler, and ${\Sigma}-{\Delta}$ modulator. An NP-core type VCO is adopted to optimize both phase noise and power consumption. Dynamic D-F/Fs with no static DC current are employed in designing the low-power prescaler circuit. The ${\Sigma}-{\Delta}$ modulator is designed using a modulus mapping circuit for reducing hardware complexity and power consumption. The designed frequency synthesizer which was fabricated using a $0.18{\mu}m$ CMOS process consumes 7.9mA from a single 1.8V supply voltage. The experimental results show that a phase noise of -118dBc/Hz at 1MHz offset, the reference spur of -70dBc at 25MHz offset, and the channel switching time of $15{\mu}s$ over 25MHz transition have been achieved. The designed chip occupies an area of $1.16mm^2$ including pads where the core area is only $0.64mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.2
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• pp.25-34
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• 2010

This paper proposed a high-speed voltage-controlled ring-oscillator(VCRO) using a frequency doubling technique. The design of the proposed oscillator has been based on TSMC 0.18um 1.8V CMOS technology. The frequency doubling technique is achieved by AND-OR operations with 4 signals which have $90^{\circ}$ phase difference one another in one cycle. The proposed technique has been implemented using a 4-stage differential oscillator compose of differential latched inverters and NAND gates for AND and OR operations. The differential ring-oscillator can generate 4 output signals, which are $90^{\circ}$ out-of-phase one another, with low phase noise. The ANP-OR operations needed in the proposed technique are implemented using NAND gates, which is more area-efficient and provides faster switching speed than using NOR gates. Simulation results show that the proposed, VCRO operates in the frequency range of 3.72 GHz to 8 GHz with power consumption of 4.7mW at 4GHz and phase noise of ~-86.79dBc/Hz at 1MHz offset. Therefore, the proposed oscillator demonstrates superior performance compared with previous high-speed voltage-controlled ring-oscillators and can be used to build high-performance frequency synthesizers and phase-locked loops for radio-frequency applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.65-72
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• 2008

This paper proposes a new dual-loop digital PLL(DPLL) using seamless frequency tracking methods. The dual-loop construction, which is composed of the coarse and fine loop for fast locking time and a switching noise suppression, is used successive approximation register technique and TDC. The proposed DPLL in order to compensate the quality of jitter which follows long-term of input frequency is newly added cord conversion frequency tracking method. Also, this DPLL has VCO circuitry consisting of digitally controlled V-I converter and current-control oscillator (CCO) for robust jitter characteristics and wide lock range. The chip is fabricated with Dongbu HiTek $0.18-{\mu}m$ CMOS technology. Its operation range has the wide operation range of 0.4-2GHz and the area of $0.18mm^2$. It shows the peak-to-peak period jitter of 2 psec under no power noise and the power dissipation of 18mW at 2GHz through HSPICE simulation.