• Title/Summary/Keyword: Switching Block

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Design of Programmable 14GHz Frequency Divider for RF PLL (RF PLL용 프로그램 가능한 14GHz 주파수분할기의 설계)

  • Kang, Ho-Yong;Chai, Sang-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.1
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    • pp.56-61
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    • 2011
  • This paper describes design of a programmable frequency synthesizer for RF PLL with $0.18{\mu}m$ silicon CMOS technology being used as an application of the UWB system like MBOA. To get good performance of speed and noise super dynamic circuits was used, and to get programmable division ratio switching circuits was used. Especially to solve narrow bandwidth problem of the dynamic circuits load resistance value of unit divider block was varied. Simulation results of the designed circuit shows very fast and wide operation characteristics as 1~14GHz frequency range.

Integrated Current-Mode DC-DC Buck Converter with Low-Power Control Circuit

  • Jeong, Hye-Im;Lee, Chan-Soo;Kim, Nam-Soo
    • Transactions on Electrical and Electronic Materials
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    • v.14 no.5
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    • pp.235-241
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    • 2013
  • A low power CMOS control circuit is applied in an integrated DC-DC buck converter. The integrated converter is composed of a feedback control circuit and power block with 0.35 ${\mu}m$ CMOS process. A current-sensing circuit is integrated with the sense-FET method in the control circuit. In the current-sensing circuit, a current-mirror is used for a voltage follower in order to reduce power consumption with a smaller chip-size. The N-channel MOS acts as a switching device in the current-sensing circuit where the sensing FET is in parallel with the power MOSFET. The amplifier and comparator are designed to obtain a high gain and a fast transient time. The converter offers well-controlled output and accurately sensed inductor current. Simulation work shows that the current-sensing circuit is operated with an accuracy of higher than 90% and the transient time of the error amplifier is controlled within $75{\mu}sec$. The sensing current is in the range of a few hundred ${\mu}A$ at a frequency of 0.6~2 MHz and an input voltage of 3~5 V. The output voltage is obtained as expected with the ripple ratio within 1%.

The Influence on Traction Return Current by Pantograph Detachment Frequency of High-speed Train (고속철도차량의 이선빈도가 귀선전류에 미치는 영향)

  • Lee, Sung-Gyen;Cho, Young-Maan;Ko, Kwang-Cheol
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.28 no.9
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    • pp.8-13
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    • 2014
  • Currently it is major problem of electric railway with increasing drive speed such as the arc generated by the pantograph detachment and the distortion current in the motor-block high speed switching. When physical contact between the pantograph and the catenary line is separated, the pantograph detachment arcing occurs and it makes up the conductive noise to the return feeder. We made the EMTP modeling of the railway traction system and the pantograph arc by circuit elements and switches. The influence of pantograph detachment frequency is investigated by changing some frequencies. The over-current occurs in each detachment and it oscillates some time at beginning and stabilizes gradually. The magnitude of over-current is decided by instantaneous value of existing traction return current. If the detachment occurs at a point of peak value or distortion current, the over-current will be more harmful to the power systems connected with the return feeder and will become to arise with increasing detachment frequency.

A Study on Standby Power and Reduced Power Consumption Control System for High-efficiency Module (대기전력 및 소비전력 절감을 위한 고효율 모듈제어 시스템에 관한 연구)

  • Lee, Myung-Hwan;Park, Yung-Teak;Chung, Hun-Suk;Kang, Ey-Goo
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.25 no.5
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    • pp.334-339
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    • 2012
  • A study on electrical and electronic equipment will occur in the atmosphere, which is essential to cut the power to prevent the waste of power by power measurement technology development and to develop the technology to do this operation is the main core of standby power to detect and block it and return the configured for software and hardware, while the actual construction to ensure stability through field testing and debugging of problems improved accordingly, as well as ease of installation and so it could be done while the test. In addition, in terms of basic hardware switching of standby power when blocking, reducing stress and ensure stable operation and circuit design, power off and back to ensure stable operation even when a protection circuit is applied.

LED Backlight Driving Circuits and Dimming Method

  • Kwon, Oh-Kyong;Jung, Young-Ho;Lee, Yong-Hak;Cho, Hyun-Suk;Nam, Ki-Soo;In, Hai-Jung
    • Journal of Information Display
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    • v.11 no.4
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    • pp.173-181
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    • 2010
  • In this paper, light-emitting-diode (LED) backlight driving circuits and dimming method for medium-sized and large liquid crystal displays (LCDs) are proposed. The double loop control method, the intelligent-phase-shifted PWM dimming method, the fast-switching current regulator, and the current matching techniques are proposed to improve not only the current regulation characteristics and the power efficiency but also the current matching characteristics and the transient response of the LED current. The brightness of the backlight using the proposed local dimming method was determined from the histogram of the local block to reduce the power consumption of the backlight without image distortion. The measured maximum power efficiency of the LED backlight driving circuit for medium-sized LCDs was 90%, and the simulation results showed an 88% maximum power efficiency of the LED backlight driving circuit for large LCDs. The maximum backlight power-saving ratio of the proposed dimming method was 41.7% in the simulation with a high-contrast image. The experiment and simulation results showed that the performance of LEDs as LCD backlight units (BLUs) improved with the proposed circuits and method.

A design of 32-bit RISC core for PDA (PDA를 위한 32비트 RISC 코어의 설계)

  • 곽승호;최병윤;이문기
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.22 no.10
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    • pp.2136-2149
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    • 1997
  • This paper describes RISC core that has been designed for embedded and protable applications such as PDA or PCS. This RISC processor offers low power consumption and fast context switching. Processor performance is improved by using conditional instruction execution, block data transfer instruction, and multiplication instruction. This architecture is based on RISC principles. The processor adopts 3-stage instruction execution pipeline and has achieved single cycle execution using a 2-phase 40MHz clock. This results in a high instruction throughput and real-time interrupt response. This chip is implemented with $0.6{\mu}m$ triple metal CMOS technology and consists of about 88K transistors. The estimated power dissipation is 179mW.

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A Study on the computer-aided synthesis of TANT network (TANT회로망의 계산기 이용 합성에 관한 연구)

  • 안광선;박규태
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.17 no.6
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    • pp.51-57
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    • 1980
  • Any switching function can be constructed with universal building block of MAND gate. Threelevel AND-NOT logic networks with only true inputs are called TANT networks. Systematic approach to TANT minimization starts from the UF type minterm with the smallest subscript and ends when UF type minterms are all covered. Optinal PEI is composed of CPPI or EPPi without C-C table. The algorithm in this work is usful in solving TANT optimization porblem of four or five variables by hand solution. When variable are six or more, it is required to be solved by computer, A CAD software package of this algorithm with FORTRAN IV language is made to solve such problems.

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Adaptive Decoding Scheme of Concatenated Codes for Frequency-Hopped Spread-Spectrum Communications with a Pulse-Burst Jamming (펄스형 Jamming 신호가 존재하는 주파수 도약 대역확산 통신환경에서 쇄상부호 시스템의 적응 복호화 방식)

  • 김정곤;김성대;김형명
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.19 no.7
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    • pp.1234-1243
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    • 1994
  • We propose an adaptive decoding scheme for a concatenated codes with frequency-hopped spread-spectrum communication system in the presence of a pulse-burst jammer and its performance is analyzed. Concatenated coding system employing binary inner code and Reed-Solomon outer code is investigated and the use of side information is allowed to decode both erasures and errors. Our scheme makes the decoder adapts to the level of jamming by switching between two decoding modes such that the overall block error probability can be reduced. It is shown that the proposed decoding scheme yields a significant performance improvement over a conventional decoding scheme.

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Modified Adaptive Gaussian Filter for Removal of Salt and Pepper Noise

  • Li, Zuoyong;Tang, Kezong;Cheng, Yong;Chen, Xiaobo;Zhou, Chongbo
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.9 no.8
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    • pp.2928-2947
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    • 2015
  • Adaptive Gaussian filter (AGF) is a recently developed switching filter to remove salt and pepper noise. AGF first directly identifies pixels of gray levels 0 and 255 as noise pixels, and then only restored noise pixels using a Gaussian filter with adaptive variance based on the estimated noise density. AGF usually achieves better denoising effect in comparison with other filters. However, AGF still fails to obtain good denoising effect on images with noise-free pixels of gray levels 0 and 255, due to its severe false alarm in its noise detection stage. To alleviate this issue, a modified version of AGF is proposed in this paper. Specifically, the proposed filter first performs noise detection via an image block based noise density estimation and sequential noise density guided rectification on the noise detection result of AGF. Then, a modified Gaussian filter with adaptive variance and window size is used to restore the detected noise pixels. The proposed filter has been extensively evaluated on two representative grayscale images and the Berkeley image dataset BSDS300 with 300 images. Experimental results showed that the proposed filter achieved better denoising effect over the state-of-the-art filters, especially on images with noise-free pixels of gray levels 0 and 255.

The signal system operation plan research for a Tilting train introduction (국내 틸팅열차 도입을 위한 신호시스템 운영방안 연구)

  • Lee, Hoon-Koo;Lee, Nam-Hyeong;Lee, Soo-Hwan;Lee, Young-Ho;Baek, Jong-Hyen
    • Proceedings of the KSR Conference
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    • 2009.05a
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    • pp.1999-2004
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    • 2009
  • Since 2003, the domestic ground signalling system of the Kyeongbu and Honam lines has been steadily improving with the introduction of the ATP system and application of the system to the train is actively being pursued for 2009 target. Therefore, new ground signalling systems are being installed to the trains and track conditions to control the train speed to a maximum of either 80km/h, 120km/h, 150km/h, or 160km/h. As well, considering safe breaking distance, block signalling has been installed and also the change over times of the track switching device has been adjusted according to the train speed. Since the new Tilting trains will be running faster than present trains, at speeds over 180 km/h, we anticipate that there will be problems with present signalling facilities. Therefore this paper attempts to examine the various problems with the interface between the ATP signalling system and the new Tilting trains and also it will propose the most effective operating plan based upon case studies of successful foreign operations.

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