• Title/Summary/Keyword: Switching Activity

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PCRAM Flip-Flop Circuits with Sequential Sleep-in Control Scheme and Selective Write Latch

  • Choi, Jun-Myung;Jung, Chul-Moon;Min, Kyeong-Sik
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.13 no.1
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    • pp.58-64
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    • 2013
  • In this paper, two new flip-flop circuits with PCRAM latches that are FF-1 and FF-2, respectively, are proposed not to waste leakage during sleep time. Unlike the FF-1 circuit that has a normal PCRAM latch, the FF-2 circuit has a selective write latch that can reduce the switching activity in writing operation to save switching power at sleep-in moment. Moreover, a sequential sleep-in control is proposed to reduce the rush current peak that is observed at the sleep-in moment. From the simulation of storing '000000' to the PCRAM latch, we could verify that the proposed FF-1 and FF-2 consume smaller power than the conventional 45-nm FF if the sleep time is longer than $465{\mu}s$ and $95{\mu}s$, respectively, at $125^{\circ}C$. For the rush current peak, the sequential sleep-in control could reduce the current peak as much as 77%.

Two Phase Clocked Adiabatic Static CMOS Logic and its Logic Family

  • Anuar, Nazrul;Takahashi, Yasuhiro;Sekine, Toshikazu
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.10 no.1
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    • pp.1-10
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    • 2010
  • This paper proposes a two-phase clocked adiabatic static CMOS logic (2PASCL) circuit that utilizes the principles of adiabatic switching and energy recovery. The low-power 2PASCL circuit uses two complementary split-level sinusoidal power supply clocks whose height is equal to $V_{dd}$. It can be directly derived from static CMOS circuits. By removing the diode from the charging path, higher output amplitude is achieved and the power consumption of the diode is eliminated. 2PASCL has switching activity that is lower than dynamic logic. We also design and simulate NOT, NAND, NOR, and XOR logic gates on the basis of the 2PASCL topology. From the simulation results, we find that 2PASCL 4-inverter chain logic can save up to 79% of dissipated energy as compared to that with a static CMOS logic at transition frequencies of 1 to 100 MHz. The results indicate that 2PASCL technology can be advantageously applied to low power digital devices operated at low frequencies, such as radio-frequency identifications (RFIDs), smart cards, and sensors.

Variable Sampling Window Flip-Flops for High-Speed Low-Power VLSI (고속 저전력 VLSI를 위한 가변 샘플링 윈도우 플립-플롭의 설계)

  • Shin Sang-Dae;Kong Bai-Sun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.8 s.338
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    • pp.35-42
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    • 2005
  • This paper describes novel flip-flops with improved robustness and reduced power consumption. Variable sampling window flip-flop (VSWFF) adjusts the width of the sampling window according to input data, providing robust data latching as well as shorter hold time. The flip-flop also reduces power consumption for higher input switching activities as compared to the conventional low-power flip-flop. Clock swing-reduced variable sampling window flip-flop (CSR-VSWFF) reduces clock power consumption by allowing the use of a small swing clock. Unlike conventional reduced clock swing flip-flops, it requires no additional voltage higher than the supply voltage, eliminating design overhead related to the generation and distribution of this voltage. Simulation results indicate that the proposed flip-flops provide uniform latency for narrower sampling window and improved power-delay product as compared to conventional flip-flops. To evaluate the performance of the proposed flip-flops, test structures were designed and implemented in a $0.3\mu m$ CMOS process technology. Experimental result indicates that VSWFF yields power reduction for the maximum input switching activity, and a synchronous counter designed with CSR-VSWFF improves performance in terms of power consumption with no use of extra voltage higher than the supply voltage.

Enzyme Activities Related to the Methanol Oxidation of Mycobacterium sp. strain JCl DSM 3803

  • Youngtae Ro;김응빈;김영민
    • Korean Journal of Microbiology
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    • v.38 no.4
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    • pp.209-209
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    • 2002
  • Mycobacterium sp. strain JCl DSM 3803 grown in methanol showed no methanol dehydrogenase or oxidase activities found in mast methylotrophic bacteria and yeasts, respectively. Even though the methanol-grown cells exhibited a little methanol-dependent oxidation by cytochrome c-dependent methanol dehydrogenase and alcohol dehydrogenase, they were not the key enzymes responsible for the methanol oxidation of the cells, in that the cells contained no c-type cytochrome and the methanol oxidizing activity from the partially purified alcohol dehydrogenase was too low, respectively. In substrate switching experiments, we found that only a catalase-peroxidase among the three types of catalase found in glucose-grown cells was highly expressed, in the methanol-grown cells and that its activity was relatively high during the exponential growth phase in Mycobacterium sp. JCl. Therefore, we propose that catalase-peroxidase is an essential enzyme responsible for the methanol metabolism directly Of indirectly in Mycobacterium sp. JCl.

Digital Sequence CPLD Technology Mapping Algorithm

  • Youn, Choong-Mo
    • Journal of information and communication convergence engineering
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    • v.5 no.2
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    • pp.131-135
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    • 2007
  • In this paper, The proposed algorithm consists of three steps. In the first step, TD(Transition Density) calculation has to be performed. a CLB-based CPLD low-power technology mapping algorithm considered a Trade-off is proposed. To perform low-power technology mapping for CPLDs, a given Boolean network has to be represented in a DAG. Total power consumption is obtained by calculating the switching activity of each node in a DAG. In the second step, the feasible clusters are generated by considering the following conditions: the number of inputs and outputs, the number of OR terms for CLB within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. In the final step, low-power technology mapping based on the CLBs packs the feasible clusters. The proposed algorithm is examined using SIS benchmarks. When the number of OR terms is five, the experiment results show that power consumption is reduced by 30.73% compared with TEMPLA, and by 17.11 % compared with PLA mapping.

A Study on Low Power Force-Directed scheduling for Optimal module selection Architecture Synthesis (최적 모듈 선택 아키텍쳐 합성을 위한 저전력 Force-Directed 스케쥴링에 관한 연구)

  • Choi Ji-young;Kim Hi-seok
    • Proceedings of the IEEK Conference
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    • 2004.06b
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    • pp.459-462
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    • 2004
  • In this paper, we present a reducing power consumption of a scheduling for module selection under the time constraint. A a reducing power consumption of a scheduling for module selection under the time constraint execute scheduling and allocation for considering the switching activity. The focus scheduling of this phase adopt Force-Directed Scheduling for low power to existed Force-Directed Scheduling. and it constructs the module selection RT library by in account consideration the mutual correlation of parameters in which the power and the area and delay. when it is, in this paper we formulate the module selection method as a multi-objective optimization and propose a branch and bound approach to explore the large design space of module selection. Therefore, the optimal module selection method proposed to consider power, area, delay parameter at the same time. The comparison experiment analyzed a point of difference between the existed FDS algorithm and a new FDS_RPC algorithm.

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Systematic Quality Assurance Activity for TDX-10 ISDN Switching System (TDX-10 ISDN 시스템의 시험 및 평가분석 체계화에 따른 품질보증 활동)

  • Lee, Haeryong;Jeong, Taegwon
    • Journal of Korean Society for Quality Management
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    • v.23 no.1
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    • pp.127-141
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    • 1995
  • 대용량 ISDN(Integrated Services Digital Network)용 전전자 교환기 TDX-10 연구개발 사업의 궁극적 목적은 미래 통신망이 요구하는 다양한 음성 및 비음성 정보통신 서비스를 제공하고 정보의 교환, 가공, 축적 및 처리에 고도의 융통성을 부여할 수 있는 국내표준 전전자 교환기를 개발하여 통신투자의 경제적 통신운영기술 자립화를 달성하는데 있다. 현재 대용량 전전자 교환기인 TDX-10 ISDN의 상용화 단계의 마무리 업무가 진행중이며, 통신서비스의 다양화, 광대역화, 고속화를 위한 광대역통신망의 주축이 되는 ATM교환기가 개발중에 있다. 본 고에서는 TDX-10 ISDN 시스템개발단계에서 구현된 시스템 시험수행 과정 및 평가작업을 토대로한 체계적이며 전략적인 품질보증 활동에 관해 기술하였으며, 신뢰성 있는 시험결과를 도출할 수 있는 다양한 시험관리 기법과 그 결과를 분석하고 차후 시험 및 보완작업을 위한 제반 활동체계가 소개된다.

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Chemical and Electrochemical Synthesis of Highly Conductive and Processable PolyProDOP-alkyl Derivatives

  • Cho, Youn-Kyung;Pyo, Myoung-Ho;Zong, Kyu-Kwan
    • Journal of the Korean Electrochemical Society
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    • v.13 no.1
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    • pp.57-62
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    • 2010
  • New monomers, possessing various alkyl substituents on propylene dioxypyrrole, were synthesized. The monomers could be easily polymerized to produce highly conductive and soluble polymers. The corresponding polymers showed excellent solubility, retaining electrochemical and optical properties of their parent polymer [poly(propylene dioxypyrrole)]. The conductivities of chemically prepared polymers were quite high in a range of 20 and $60\;Scm^{-1}$. Solubility of the polymer in a common organic solvent was as high as no polymer is deposited on an electrode. The redox potentials of the electrochemically prepared polymers revealed quite stable electro-activity during repeated redox switching up to 500 times. The optoelectrochemistry studies also showed distinct color changes of the polymers upon changing the doping state, indicating strong absorption peaks at 400~600 nm in reduced states and complete bleaching in fully oxidized states.

An Energy-Efficient 64-bit Prefix Adder based on Semidynamic and Bypassing Structures

  • Hwang, Jaemin;Choi, Seongrim;Nam, Byeong-Gyu
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.15 no.1
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    • pp.150-153
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    • 2015
  • An energy-efficient 64-bit prefix adder is proposed for micro-server processors based on both semidynamic and bypassing structures. Prefix adders consist of three main stages i.e. propagate-generate (PG) stage, carry merge (CM) tree, and sum generators. In this architecture, the PG and CM stages consume most of the power because these are based on domino circuits. This letter proposes a semidynamic PG stage for its energy-efficiency. In addition, we adopt the bypassing structure on the CM tree to reduce its switching activity. Experimental results show 19.1% improvement of energy efficiency from prior art.

Attention Occurrence of Agent and its Switching of Context (에이전트의 주의발생과 그에 따른 컨텍스트의 변화)

  • Hong, Chang-Seob;Park, Jong-Hee
    • Proceedings of the Korea Contents Association Conference
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    • 2007.11a
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    • pp.788-791
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    • 2007
  • In order that An agent acts activity that makes sense corresponding to a variety of event and behavior, attention maybe occur according to perception, personality and desire. As a result contexts are switched while this attention is changed. In this paper. We propose the processing algorithm of the attention and corresponding contexts to it that are switched.

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