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Digital Sequence CPLD Technology Mapping Algorithm  

Youn, Choong-Mo (School of Information Electroniics Seoil College)
Publication Information
Journal of information and communication convergence engineering / v.5, no.2, 2007 , pp. 131-135 More about this Journal
Abstract
In this paper, The proposed algorithm consists of three steps. In the first step, TD(Transition Density) calculation has to be performed. a CLB-based CPLD low-power technology mapping algorithm considered a Trade-off is proposed. To perform low-power technology mapping for CPLDs, a given Boolean network has to be represented in a DAG. Total power consumption is obtained by calculating the switching activity of each node in a DAG. In the second step, the feasible clusters are generated by considering the following conditions: the number of inputs and outputs, the number of OR terms for CLB within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. In the final step, low-power technology mapping based on the CLBs packs the feasible clusters. The proposed algorithm is examined using SIS benchmarks. When the number of OR terms is five, the experiment results show that power consumption is reduced by 30.73% compared with TEMPLA, and by 17.11 % compared with PLA mapping.
Keywords
CPLD; Low-power technology mapping; Trade-off;
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Times Cited By KSCI : 1  (Citation Analysis)
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