[KSCI] Korea Science Citation Index Service

http://dx.doi.org/10.5573/JSTS.2015.15.1.150

An Energy-Efficient 64-bit Prefix Adder based on Semidynamic and Bypassing Structures

Hwang, Jaemin (Department of Computer Science and Engineering, Chungnam National University)
Choi, Seongrim (Department of Computer Science and Engineering, Chungnam National University)
Nam, Byeong-Gyu (Department of Computer Science and Engineering, Chungnam National University)

Publication Information

JSTS:Journal of Semiconductor Technology and Science / v.15, no.1, 2015 , pp. 150-153 More about this Journal

Abstract

An energy-efficient 64-bit prefix adder is proposed for micro-server processors based on both semidynamic and bypassing structures. Prefix adders consist of three main stages i.e. propagate-generate (PG) stage, carry merge (CM) tree, and sum generators. In this architecture, the PG and CM stages consume most of the power because these are based on domino circuits. This letter proposes a semidynamic PG stage for its energy-efficiency. In addition, we adopt the bypassing structure on the CM tree to reduce its switching activity. Experimental results show 19.1% improvement of energy efficiency from prior art.

Keywords

Semidynamic; bypassing; prefix adder; propagate-generate; carry merge;

Citations & Related Records

Reference

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