• Journal of Power Electronics
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• v.17 no.6
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• pp.1391-1401
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• 2017

In this paper, a secondary resonance half-bridge dc-dc converter with an inductive output filter is presented. The primary side of such a converter utilizes asymmetric pulse width modulation (APWM) to achieve zero-voltage switching (ZVS) of the switches, and clamps the voltage of the switch to the input voltage. In addition, zero current switching (ZCS) of the output diode is achieved by a half-wave rectifier circuit with a filter inductor and a resonant branch in the secondary side of the proposed converter. Thus, the switching losses and diode reverse-recovery losses are eliminated, and the performance of the converter can be improved. Furthermore, an inductive output filter exists in the converter reduce the output current ripple. The operational principle, performance analysis and design equation of this converter are given in this paper. The analysis results show that the output diode voltage stress is independent of the duty cycle, and that the voltage gain is almost linear, similar to that of the isolation Buck-type converter. Finally, a 200V~380V input, 24V/2A output experimental prototype is built to verify the theoretical analysis.

• Journal of Convergence for Information Technology
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• v.9 no.9
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• pp.38-43
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• 2019

In this paper, a method of inputting one analog input and two digital switch inputs by using one analog port of microcontroller embedded in IoT device was proposed. In this method, the upper limit and the lower limit of the input voltage range of the analog input port are determined, and the analog input voltage is input to this interval. The digital switches are configured to exceed the boundaries of the upper and lower limits, respectively. To verify the performance of the proposed method, an experimental circuit was constructed and tested using a microcontroller. As a result, all three inputs can be sensed using a single analog port, thus confirming that the three required input ports are reduced to one input port, ie, 33%.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.16 no.9
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• pp.2846-2866
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• 2022

Caenorhabditis elegans exhibits sophisticated chemotaxis behavior through two parallel strategies, klinokinesis and klinotaxis, executed entirely by a small nervous circuit. It is therefore suitable for inspiring fast and energy-efficient solutions for autonomous navigation. As a random search strategy, the Lévy walk is optimal for diverse animals when foraging without external chemical cues. In this study, by combining these biological strategies for the first time, we propose a spiking neural network model for search and contour tracking of specific concentrations of environmental variables. Specifically, we first design a klinotaxis module using spiking neurons. This module works in conjunction with a klinokinesis module, allowing rapid searches for the concentration setpoint and subsequent contour tracking with small deviations. Second, we build a random exploration module. It generates a Lévy walk in the absence of concentration gradients, increasing the chance of encountering gradients. Third, considering local extrema traps, we develop a termination module combined with an escape module to initiate or terminate the escape in a timely manner. Experimental results demonstrate that the proposed model integrating these modules can switch strategies autonomously according to the information from a single sensor and control steering through output spikes, enabling the model worm to efficiently navigate across various scenarios.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.12
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• pp.99-108
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• 2015

The embedded microcontroller which is operated by the logic gates synchronized on the clock pulse, is gradually used as main controller of mission-critical systems. Severe electrical situations such as high voltage/frequency surge may cause malfunctioning of the clock source. The tolerant system operation is required against the various external electric noise and means the robust design technique is becoming more important issue in system clock failure problems. In this paper, we propose on-chip backup clock change architecture for the automatic clock failure detection. For the this, we adopt the edge detector, noise canceller logic and glitch-free clock changer circuit. The implemented edge detector unit detects the abnormal low-frequency of the clock source and the delay chain circuit of the clock pulse by the noise canceller can cancel out the glitch clock. The externally invalid clock source by detecting the emergency status will be switched to back-up clock source by glitch-free clock changer circuit. The proposed circuits are evaluated by Verilog simulation and the fabricated IC is validated by using test equipment electrical field radiation noise

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.9
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• pp.834-843
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• 2016

In this paper, the design of a PIN diode S-band transfer-type SP4T including its driver circuit is presented. Each path of the SP4T is composed of the cascade connection of series-shunt PIN diodes to improve the isolation performance. The SP4T is implemented using chip type PIN diodes and a 20 mil AIN substrate fabricated using thin film technology. The driver circuit for the SP4T is designed using a multiplexer and four NMOS-PMOS push-pull pair. From on-wafer measurement, the fabriacted SP4T shows a maximum insertion loss of 1.1 dB and a minimum isolation of 41 dB. The time performance of the driver circuit is evaluated using the packaged PIN diodes with the identical PIN diode chip, and the transition time for on-off and off-on are below 100 nsec. For an input power level of 150 W, the measured insertion loss and isolation are close to those of the on-wafer measurement taking into consideration of the coaxial package mismatch and insertion loss.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.8
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• pp.38-44
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• 2007

This paper describes a 12 bit 80MHz CMOS D/A converter for wireless transceiver. Proposed circuit in the paper employes segmented structure which consists of four stage 3bit thermometer decoders. Proposed D/A converter is manufactured 0.35um CMOS n-well digital standard process and measurement results show a ${\pm}1.36SB/{\pm}0.62LSB$ of INL/DNL and $46pV{\cdot}s$ of glitch energy. SNR and SFDR are measured to be 58.5dB and 64.97dB @ Fs=80MHz and Fin=19MHz with a total power consumption of 99mW. Such results proved that our work has low power consumption, high linearity, low glitch and improved dynamic performance. Therefore, our work can be appled to various high speed and high performance circuits.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.4
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• pp.913-920
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• 2011

In this paper, a logic process based 1-kbit EEPROM IP for RFID tag chips of 900MHz is designed. The cell array of the designed 1-kbit EEPROM IP is arranged in a form of four blocks of 16 rows x 16 columns, that is in a two-dimensional arrangement of one-word EEPROM phantom cells. We can reduce the IP size by making four memory blocks share CG (control gate) and TG (tunnel gate) driver circuits. We propose a TG switch circuit to supply respective TG bias voltages according to operational modes and to keep voltages between devices within 5.5V in terms of reliability in order to share the TG driver circuit. Also, we can reduce the power consumption in the read mode by using a partial activation method to activate just one of four memory blocks. Furthermore, we can reduce the access time by making BL (bit line) switching times faster in the read mode from reduced number of cells connected to each column. We design and compare two 1-kbit EEPROM IPs, two blocks of 32 rows ${\times}$ 16 columns and four blocks of 16 rows ${\times}$ 16 columns, which use Tower's $0.18{\mu}m$ CMOS process. The four-block IP is smaller by 11.9% in the layout size and by 51% in the power consumption in the read mode than the two-block counterpart.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.9
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• pp.4177-4185
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• 2012

LEDs are becoming the most suitable candidate replacing traditional fluorescent lamps because of its eco-friendly characteristics. LEDs are also actively used to design green building system and to make outdoor billboard as a back-light system due to its high energy efficiency. In this paper, we have developed AC direct driver for $12{\times}12$ FLB(flexible LED board) and LED flat light without SMPS. It has LID-PC-R101B driver IC that can support the high power factor and be composed of LED switching circuit in group. Also, an elaborate system designs can guarantee a high luminous efficiency, a high reliability and a low power consumption. The proposed FLB has the ultra slim shape of $450{\times}450$ mm, width of 4 mm and weight of 280 g. In the end, we have developed a prototype of FLB for billboard and flat light for room lighting with AC direct driver iposrder to verify the performance of the proposed system.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.8
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• pp.461-465
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• 2016

n-type silicon shows the better tolerance towards metal impurities with a higher minority carrier lifetime compared to p-type silicon substrate. Due to better lifetime stability as compared to p-type during illumination made the photovoltaic community to switch toward n-type wafers for high efficiency silicon solar cells. We fabricated the front electrode of the n-type solar cell with AgAl paste. The electrodes characteristics of the AgAl paste depend on the contact junction depth that is closely related to the firing temperature. Metal contact depth with p+ emitter, with optimized depth is important as it influence the resistance. In this study, we optimize the firing condition for the effective formation of the metal depth by varying the firing condition. The firing was carried out at temperatures below $670^{\circ}C$ with low contact depth and high contact resistance. It was noted that the contact resistance was reduced with the increase of firing temperature. The contact resistance of $5.99m{\Omega}cm^2$ was shown for the optimum firing temperature of $865^{\circ}C$. Over $900^{\circ}C$, contact junction is bonded to the Si through the emitter, resulting the contact resistance to shunt. we obtained photovoltaic parameter such as fill factor of 76.68%, short-circuit current of $40.2mA/cm^2$, open-circuit voltage of 620 mV and convert efficiency of 19.11%.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.49 no.12
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• pp.1019-1025
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• 2021

In nearly all space environments, the solar cell degradation is dominated by protons[1]. Even through a GEO orbit lines in the electron radiation belts, the protons emitted from any solar event will still dominate the degradation[1]. Since COMS launch on June 26 2010, the proton events with the fluence of more than approximately 30 times the average level of perennial observations were observed between January 23 - 29 2012 and March 07 - 14 2012[16]. This paper studies the solar cell degradation by solar proton events in January and March 2012 for the open circuit voltage(Voc) of a witness cell and the short circuit current(Isc) of a section connected to a shunt switch. To evaluate the performance of solar cell, the flight data of voltage and current are corrected to the temperature, the Earth-Sun distance and the Sun angle and then compare with the solar cell characteristics at BOL. The Voc voltage dropped about 23.6mV compare after the March 2012 proton events to before the January 2012 proton events. The Voc voltage dropped less than 1% at BOL, which is 2575mV. The Isc current decreased negligible, as expected, in the March 2012 proton events.