• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2018년도 춘계학술대회
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• pp.171-172
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• 2018

Dual gate L-shaped tunnel field-effect-transistor (DG-LTFET) is presented in this study. DG-LTFET achieves near vertical subthreshold slope (SS) and its ON current is also found to be higher then both conventional TFET and LTFET. This device could serve as a potential replacement for conventional complimentary metal-oxide-semiconductor (CMOS) technology.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권5호
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• pp.530-537
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• 2013

An explicit surface potential calculation method of gate-all-around MOSFET (GAAMOSFET) devices which takes into account both interface trap charge and varying doping levels is presented. The results of the method are extensively verified by numerical simulation. Results from the model are used to find qualitative and quantitative effect of interface trap charge on subthreshold slope (SS) of GAAMOSFET devices. Further, design constraints of GAAMOSFET devices with emphasis on the effect of interface trap charge on device SS performance are investigated.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권3호
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• pp.360-369
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• 2012

The causes of showing different subthreshold slopes (SS) in programmed and erased states for two different charge trap flash (CTF) memory devices, SONOS type flash memory with gate-all-around (GAA) structure and TANOS type NAND flash memory with planar structure were investigated. To analyze the difference in SSs, TCAD simulation and low-frequency noise (LFN) measurement were fulfilled. The device simulation was performed to compare SSs considering the gate electric field effect to the channel and to check the localized trapped charge distribution effect in nitride layer while the comparison of noise power spectrum was carried out to inspect the generation of interface traps ($N_{IT}$). When each cell in the measured two memory devices is erased, the normalized LFN power is increased by one order of magnitude, which is attributed to the generation of $N_{IT}$ originated by the movement of hydrogen species ($h^*$) from the interface. As a result, the SS is degraded for the GAA SONOS memory device when erased where the $N_{IT}$ generation is a prominent factor. However, the TANOS memory cell is relatively immune to the SS degradation effect induced by the generated $N_{IT}$.

• 전자공학회논문지
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• 제49권12호
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• pp.179-183
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• 2012

3차원 시뮬레이션을 이용하여 터널링 전계효과 트랜지스터(TFET)의 불순물 분포 변동(RDF) 효과에 대해 살펴보았다. TFET의 RDF 효과는 매우 낮은 바디 도핑 농도 때문에 많이 논의되지 않았다. 하지만 본 논문에서는 임의로 생성되고 분포되는 소스 불순물이 TFET의 문턱전압 ($V_{th}$)과 드레인 유기 전류 증가 (DICE), 문턱전압이하 기울기 (SS)의 변화를 증가시킴을 발견하였다. 또한, TFET의 RDF 효과를 감소시킬 수 있는 몇 가지 방법을 제시하였다.

• 전기전자학회논문지
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• 제23권2호
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• pp.704-709
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• 2019

본 논문에서는 다양한 열처리(annealing) 조건에서 tunneling field effect transistor(TFET)의 전기적 특성을 연구 하였다. TFET 샘플은 수소 혼합 가스(4 %) 및 중수소($D_2$) 혼합 가스 (4 %)를 사용하여 열처리를 진행하였으며 측정은 노이즈 차폐실에서 진행되었다. 실험 결과, 열처리 전과 비교하여 열처리 공정 후에 subthreshold slope(SS)이 33 mV / dec만큼 감소함을 확인할 수 있었다. 그리고 측정 온도 범위에서 온도가 증가할수록 $V_G=3V$ 조건에서 10 기압의 중수소 혼합 가스에 대해 평균 31.2 %의 노이즈가 개선됨을 확인할 수 있었다. $D_2$ 혼합 가스로 메탈 증착 후 열처리 공정(post metal annealing)을 실시한 결과, $I_D=100nA$ 조건에서 평균 30.7 %의 노이즈가 감소되었음을 확인할 수 있다.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2022년도 춘계학술대회
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• pp.560-561
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• 2022

본 논문은 Nanosheet FET(NSFET)와 FinFET의 소자 성능을 3차원 소자 시뮬레이션을 통하여 다양한 구조의 NSFET와 FinFET의 소자 시뮬레이션을 한다. NSFET와 FinFET의 전류-전압 특성을 시뮬레이션하였고, 그 전류-전압 특성으로부터 추출한 문턱전압, 문턱전압이하 기울기 등의 성능을 비교하였다. NSFET이 FinFET보다 전류-전압 특성에서 드레인 전류가 더 많이 흐르며 더 높은 문턱전압을 갖는다. 문턱전압이하 기울기는 NSFET와이 FinFET보다 더 가파른 기울기를 갖는다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권1호
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• pp.156-161
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• 2017

This work presents a novel structure for junction-less tunneling field effect transistor (JL-TFET) with a floating gate over the source region. Introduction of floating gate instead of fixed metal gate removes the limitation of fabrication process suitability. The proposed device is based on a heavily n-type-doped Si-channel junction-less field effect transistor (JLFET). A floating gate over source region and a control-gate with optimized metal work-function over channel region is used to make device work like a tunnel field effect transistor (TFET). The proposed device has exhibited excellent ID-VGS characteristics, ION/IOFF ratio, a point subthreshold slope (SS), and average SS for optimized device parameters. Electron charge stored in floating gate, isolation oxide layer and body doping concentration are optimized. The proposed JL-TFET can be a promising candidate for switching performances.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2022년도 추계학술대회
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• pp.121-122
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• 2022

본 논문은 Nanosheet FET(NSFET)와 FinFET의 구조를 갖는 소자 성능을 조사하기 위해서 3차원 소자 시뮬레이터를 이용하여 시뮬레이션한 결과를 소개한다. NSFET와 FinFET의 채널 도핑 농도에 따른 전류-전압 특성을 시뮬레이션하였고, 그 전류-전압 특성으로부터 추출한 문턱전압, 문턱전압이하 기울기 등의 성능을 비교하였다. NSFET이 FinFET보다 채널 도핑 농도에 따른 전류-전압 특성에서 드레인 전류가 더 많이 흐르며 더 높은 문턱전압을 갖는다. 문턱전압이하 기울기는 NSFET가 FinFET보다 더 가파른 기울기를 갖는다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
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• pp.163-163
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• 2015

The effect of nematic liquid crystal(5CB-4-Cyano-4'-pentylbiphenyl) on the amorphous indium gallium zinc oxide thin film transistors(a-IGZO TFTs) was investigated. Through dropping the 5CB on the a-IGZO TFT's channel layer which is deposited by RF-magnetron sputtering, properties of a-IGZO TFTs was dramatically improved. When drain bias was induced, 5CB molecules were oriented by Freedericksz transition generating positive charges to one side of dipoles. From increment of the capacitance by orientation of liquid crystals, the drain current was increased, and we analyzed these phenomena mathematically by using MOSFET model. Transfer characteristic showed improvement such as decreasing of subthreshold slope(SS) value 0.4 to 0.2 and 0.45 to 0.25 at linear region and saturation region, respectively. Furthermore, in positive bias system(PBS), prevention effect for electron trapping by 5CB liquid crystal dipoles was observed, which showing decrease of threshold voltage shift [(${\delta}V$]_TH) when induced +20V for 1~1000sec at the gate electrode.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2009년도 추계학술발표대회
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• pp.48.1-48.1
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• 2009

Performance of organic field-effect transistors (OFETs) with various temperature-cured polyacrylate(PA) copolymer as a gate insulator was studied. The PA thin film, which was cured at an optimized temperature, showed high dielectric strength (>7 MV/cm), low leakage current density ($5{\times}10^{-9}\;A/cm^2$ at 1 MV/cm) and enabled negligible hysteresis in MIS capacitor and OFET. A field-effect mobility of ${\sim}0.6\;cm^2/V\;s$, on/off current ratio (Ion/Ioff) of ${\sim}10^5$ and inverse subthreshold slope (SS) as low as 1.22 V/decwere achieved. The high dielectric strength made it possible to scale down the thickness of dielectric, and low-voltage operation of -5 V was successfully realized. The chemical changes were monitored by FT-IR. The morphology and microstructure of the pentacene layer grown on PA dielectrics were also investigated and correlated with OFET device performance.