• JSTS:Journal of Semiconductor Technology and Science
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• 제5권2호
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• pp.136-147
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• 2005

A theoretical design evaluation based on a hydrodynamic transport simulation of strained Si-SiGe on insulator (SSOI) type nMOSFETs is reported. Although, the net performance improvement is quite limited by the short channel effects, simulation results clearly show that the strained Si-SiGe type nMOSFETs are well-suited for gate lengths down to 20 nm. Simulation results show that the improvement in the transconductance with decreasing gate length is limited by the long-range Coulomb scattering. An influence of lateral and vertical diffusion of shallow dopants in the source/drain extension regions on the device performance (i.e., threshold voltage shift, subthreshold slope, current drivability and transconductance) is quantitatively assessed. An optimum layer thickness ($t_{si}$ of 5 and $t_{sg}$ of 10 nm) with shallow Junction depth (5-10 nm) and controlled lateral diffusion with steep doping gradient is needed to realize the sub-50 nm gate strained Si-SiGe type nMOSFETs.

• International journal of advanced smart convergence
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• 제1권1호
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• pp.61-64
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• 2012

The ultraviolet and visible light responsive properties of the amorphous indium gallium zinc oxide thin film transistor have been investigated. Amorphous indium gallium zinc oxide (a-IGZO) thin film transistor operate in the enhancement mode with saturation mobility of $6.99cm^2/Vs$, threshold voltage of 13.5 V, subthreshold slope of 1.58 V/dec and an on/off current ratio of $2.45{\times}10^8$. The transistor was subsequently characterized in respect of visible light and UV illuminations in order to investigate its potential for possible use as a detector. The performance of the transistor is indicates a high-photosensitivity in the off-state with a ratio of photocurrent to dark current of $5.74{\times}10^2$. The obtained results reveal that the amorphous indium gallium zinc oxide thin film transistor can be used to fabricate UV photodetector operating in the 366 nm.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권2호
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• pp.286-291
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• 2015

For highly scalable NAND flash memory applications, a compact ($4F^2/cell$) nonvolatile memory architecture is proposed and investigated via three-dimensional device simulations. The back-channel program/erase is conducted independently from the front-channel read operation as information is stored in the form of charge at the backside of the channel, and hence, read disturbance is avoided. The memory cell structure is essentially equivalent to that of the fully-depleted transistor, which allows a high cell read current and a steep subthreshold slope, to enable lower voltage operation in comparison with conventional NAND flash devices. To minimize memory cell disturbance during programming, a charge depletion method using appropriate biasing of a buried back-gate line that runs parallel to the bit line is introduced. This design is a new candidate for scaling NAND flash memory to sub-20 nm lateral dimensions.

• 센서학회지
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• 제16권4호
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• pp.313-318
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• 2007

Single-wall carbon nanotube field-effect transistors (SWCNT FETs) of top gate structure were fabricated in a conventional metal-oxide-semiconductor field effect transistor (MOSFET) with gate electrodes above the conduction channel separated from the channel by a thin $SiO_{2}$ layer. The carbon nanotubes (CNTs) directly grown using thin Fe film as catalyst by thermal chemical vapor deposition (CVD). These top gate devices exhibit good electrical characteristics, including steep subthreshold slope and high conductance at low gate voltages. Our experiments show that CNTFETs may be competitive with Si MOSFET for future nanoelectronic applications.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2014년도 추계학술대회 논문집
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• pp.254-255
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• 2014

RF magnetron sputtering법으로 증착한 비정질 IGZO 박막과 이를 Active layer로 이용한 TFT의 Transfer 특성에 대한 RF Power의 영향에 대해 연구하였다. Carrier concentration은 Sputtering 공정 중에 산소 분압으로 조절하였다. RF Power가 75에서 150W로 증가할수록 IGZO 박막의 Roughness는 12.2에서 $6.5{\AA}$ 감소하였고 Density는 6.0에서 $6.1g/cm^3$로 증가하였다. 또한, 모든 IGZO 박막은 가시광 영역에서 85% 이상의 투과율을 보였고 Optical band gap은 미세하게 감소하였다. RF Power가 증가할수록 a-IGZO TFT의 Threshold voltage는 0.9에서 7V로 증가하였고, Subthreshold slope은 0.3에서 0.8 V/decade로 증가하였다. 하지만 Mobility는 11에서 $19cm^2/V{\cdot}s$로 증가하였다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.I
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• pp.293-293
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• 2005

The differences between floating and grounded body effects in polycrystalline silicon thin-film transistors (polysilicon TFTs) are investigated by making a body contact. The floating body effects such as kink effect, subthreshold slope change, and body current characteristics are explained and modeled by impact ionization, which causes source body turn on, and activates the parasitic bipolar junction transistors (BJTs). These effects become crucial for channel lengths of 4㎛ or shorter. Our data show that making a body contact reduces kink effects significantly and identifies impact ionization mechanism in polysilicon TFTs.

• ETRI Journal
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• 제28권2호
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• pp.253-256
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• 2006

We propose a novel power metal oxide semiconductor field effect transistor (MOSFET) employing a strained-Si channel structure to improve the current drivability and on-resistance characteristic of the high-voltage MOSFET. A 20 nm thick strained-Si low field channel NMOSFET with a $0.75\;{\mu}m$ thick $Si_{0.8}Ge_{0.2}$ buffer layer improved the drive current by 20% with a 25% reduction in on-resistance compared with a conventional Si channel high-voltage NMOSFET, while suppressing the breakdown voltage and subthreshold slope characteristic degradation by 6% and 8%, respectively. Also, the strained-Si high-voltage NMOSFET improved the transconductance by 28% and 52% at the linear and saturation regimes.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.271-272
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• 2008

We fabricated a pentacene thin-film transistor with Ni/Ag source/drain electrodes. Also, we obtained similar electrical characteristics as compared with source/drain electrode with Au. This device was found to have a field-effect mobility of about 0.021 $cm^2$/Vs, a threshold voltage of -5, -7 V, an subthreshold slope of 2.0, 4.5 V/decade, and an on!off current ratio of $3.6\times10^5$, $2.0\times10^6$.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.264-264
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• 2008

We fabricated a pentacene thin-film transistor with a Polymer/$SiO_2$ Double Gate Dielectrics and obtained a device with better electrical characteristics. This device was found to have a field-effect mobility of $0.04cm^2$/Vs, a threshold voltage of -2V, an subthreshold slope of 1.3 V/decade, and an on/off current ratio of $10^7$.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2018년도 추계학술대회
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• pp.512-513
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• 2018

트랩-보조-터널링(Trap-Assisted-Tunneling; TAT)은 실제 터널링 전계 효과 트랜지스터 (TFET)의 임계 이하 기울기를 저하시키고 시뮬레이션에서 고려되어야한다. 그러나, 그 메커니즘은 라인 터널링 타입 L형 TFET(LTFET)에서는 잘 알려져 있지 않았다. 본 연구는 dynamic nonlocal Schenk 모델을 이용한 LTFET의 TAT 메커니즘을 연구한다. 이 연구에서는 터널링 이벤트를 위해서 phonon assisted and direct band가 모두 고려되었다.