• JSTS:Journal of Semiconductor Technology and Science
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• 제13권5호
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• pp.530-537
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• 2013

An explicit surface potential calculation method of gate-all-around MOSFET (GAAMOSFET) devices which takes into account both interface trap charge and varying doping levels is presented. The results of the method are extensively verified by numerical simulation. Results from the model are used to find qualitative and quantitative effect of interface trap charge on subthreshold slope (SS) of GAAMOSFET devices. Further, design constraints of GAAMOSFET devices with emphasis on the effect of interface trap charge on device SS performance are investigated.

• Transactions on Electrical and Electronic Materials
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• 제18권5호
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• pp.250-252
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• 2017

High-performance full swing logic inverters were fabricated using amorphous 1 wt% Si doped indium-zinc-oxide (a-SIZO) thin films with different channel layer thicknesses. In the inverter configuration, the threshold voltage was adjusted by varying the thickness of the channel layer. The depletion mode (D-mode) device used a TFT with a channel layer thickness of 60 nm as it exhibited the most negative threshold voltage (-1.67 V). Inverters using enhancement mode (E-mode) devices were fabricated using TFTs with channel layer thicknesses of 20 or 40 nm with excellent subthreshold slope (S.S). Both the inverters exhibited high voltage gain values of 30.74 and 28.56, respectively at $V_{DD}=15V$. It was confirmed that the voltage gain can be improved by increasing the S.S value.

• 전기전자학회논문지
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• 제23권2호
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• pp.704-709
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• 2019

본 논문에서는 다양한 열처리(annealing) 조건에서 tunneling field effect transistor(TFET)의 전기적 특성을 연구 하였다. TFET 샘플은 수소 혼합 가스(4 %) 및 중수소($D_2$) 혼합 가스 (4 %)를 사용하여 열처리를 진행하였으며 측정은 노이즈 차폐실에서 진행되었다. 실험 결과, 열처리 전과 비교하여 열처리 공정 후에 subthreshold slope(SS)이 33 mV / dec만큼 감소함을 확인할 수 있었다. 그리고 측정 온도 범위에서 온도가 증가할수록 $V_G=3V$ 조건에서 10 기압의 중수소 혼합 가스에 대해 평균 31.2 %의 노이즈가 개선됨을 확인할 수 있었다. $D_2$ 혼합 가스로 메탈 증착 후 열처리 공정(post metal annealing)을 실시한 결과, $I_D=100nA$ 조건에서 평균 30.7 %의 노이즈가 감소되었음을 확인할 수 있다.

• 전자공학회논문지
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• 제49권12호
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• pp.179-183
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• 2012

3차원 시뮬레이션을 이용하여 터널링 전계효과 트랜지스터(TFET)의 불순물 분포 변동(RDF) 효과에 대해 살펴보았다. TFET의 RDF 효과는 매우 낮은 바디 도핑 농도 때문에 많이 논의되지 않았다. 하지만 본 논문에서는 임의로 생성되고 분포되는 소스 불순물이 TFET의 문턱전압 ($V_{th}$)과 드레인 유기 전류 증가 (DICE), 문턱전압이하 기울기 (SS)의 변화를 증가시킴을 발견하였다. 또한, TFET의 RDF 효과를 감소시킬 수 있는 몇 가지 방법을 제시하였다.

• 한국산학기술학회논문지
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• 제11권5호
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• pp.1592-1596
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• 2010

IGZO (indium gallium zinc oxide) 박막트랜지스터는, 활성층 채널의 폭과 길이의 비가 고정된 경우에도, 채널 길이가 길어지면 게이트전압에 대한 드레인 전류의 특성곡선이 양의 전압 방향으로 이동하고 전계효과이동도는 낮아졌다. 채널의 길이와 폭이 고정된 상태에서는, 드레인이 전압 높은 경우에 전계효과이동도가 낮고 문턱아래 기울기가 큰 특성을 보였다. 이러한 현상은 IGZO 채널층의 일함수가 커서 소스/드레인 전극과 채널층의 접합부 띠굽음이 규소반도체의 경우와 반대방향으로 나타나는 것에 기인하는 것으로 해석된다.

• 한국전기전자재료학회논문지
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• 제16권1호
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• pp.26-32
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• 2003

Then-channel poly-Si thin-film transistors (poly-Si TFT's) formed by solid phase crystallization (SPC) method on glass were measured to obtain the electrical parameters such as of I-V characteristics, mobility, leakage current, threshold voltage, and subthreshold slope. Then, devices were analyzed to obtain the reliability and appliability on TFT-LCD with large-size and high density. In n-channel poly-Si TFT with 5$\mu\textrm{m}$/2$\mu\textrm{m}$, 8$\mu\textrm{m}$, 30$\mu\textrm{m}$ devices of channel width/length, the field effect mobilities are 111, 116, 125 $\textrm{cm}^2$/V-s and leakage currents are 0.6, 0.1, and 0.02 pA/$\mu\textrm{m}$, respectively. Low threshold voltage and subthreshold slope, and good ON-OFF ratio are shown, as well. Thus. the poly-Si TFT's used by SPC are expected to be applied on TFT-LCD with large-size and high density, which can integrate the display panel and peripheral circuit on a targe glass substrate.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권3호
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• pp.360-369
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• 2012

The causes of showing different subthreshold slopes (SS) in programmed and erased states for two different charge trap flash (CTF) memory devices, SONOS type flash memory with gate-all-around (GAA) structure and TANOS type NAND flash memory with planar structure were investigated. To analyze the difference in SSs, TCAD simulation and low-frequency noise (LFN) measurement were fulfilled. The device simulation was performed to compare SSs considering the gate electric field effect to the channel and to check the localized trapped charge distribution effect in nitride layer while the comparison of noise power spectrum was carried out to inspect the generation of interface traps ($N_{IT}$). When each cell in the measured two memory devices is erased, the normalized LFN power is increased by one order of magnitude, which is attributed to the generation of $N_{IT}$ originated by the movement of hydrogen species ($h^*$) from the interface. As a result, the SS is degraded for the GAA SONOS memory device when erased where the $N_{IT}$ generation is a prominent factor. However, the TANOS memory cell is relatively immune to the SS degradation effect induced by the generated $N_{IT}$.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권2호
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• pp.216-222
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• 2017

The most prominent challenge for MOSFET scaling is to reduce power consumption; however, the supply voltage ($V_{DD}$) cannot be scaled down because of the carrier injection mechanism. To overcome this limit, a new type of field-effect transistor using positive feedback as a carrier injection mechanism (FBFET) has been proposed. In this study we have investigated the electrical characteristics of a $Si_{1-x}Ge_x$ FBFET with one gate and one-sided $Si_3N_4$ spacer using TCAD simulations. To reduce the drain bias dependency, $Si_{1-x}Ge_x$ was introduced as a low-bandgap material, and the minimum subthreshold swing was obtained as 2.87 mV/dec. This result suggests that a $Si_{1-x}Ge_x$ FBFET is a promising candidate for future low-power devices.

• ETRI Journal
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• 제15권2호
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• pp.11-25
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• 1993

Interface trap densities at gate oxide/silicon substrate ($SiO_2/Si$) interfaces of metal oxide semiconductor field-effect transistors (MOSFETs) were determined from the substrate bias dependence of the subthreshold slope measurement. This method enables the characterization of interface traps residing in the energy level between the midgap and that corresponding to the strong inversion of small size MOSFET. In consequence of the high accuracy of this method, the energy dependence of the interface trap density can be accurately determined. The application of this technique to a MOSFET showed good agreement with the result obtained through the high-frequency/quasi-static capacitance-voltage (C-V) technique for a MOS capacitor. Furthermore, the effective substrate dopant concentration obtained through this technique also showed good agreement with the result obtained through the body effect measurement.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2022년도 춘계학술대회
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• pp.560-561
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• 2022

본 논문은 Nanosheet FET(NSFET)와 FinFET의 소자 성능을 3차원 소자 시뮬레이션을 통하여 다양한 구조의 NSFET와 FinFET의 소자 시뮬레이션을 한다. NSFET와 FinFET의 전류-전압 특성을 시뮬레이션하였고, 그 전류-전압 특성으로부터 추출한 문턱전압, 문턱전압이하 기울기 등의 성능을 비교하였다. NSFET이 FinFET보다 전류-전압 특성에서 드레인 전류가 더 많이 흐르며 더 높은 문턱전압을 갖는다. 문턱전압이하 기울기는 NSFET와이 FinFET보다 더 가파른 기울기를 갖는다.