• JSTS:Journal of Semiconductor Technology and Science
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• 제11권2호
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• pp.130-133
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• 2011

A comparative study of two capacitance methods to measure the effective channel length in deep-submicron MOSFETs has been made in detail. Since the reduction of the overlap capacitance in the accumulation region is smaller than the addition of the inner fringe capacitance at zero gate voltage, the capacitance method removing the parasitic capacitance in the accumulation region extracts a more accurate effective channel length than the method removing that at zero gate voltage.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(I)
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• pp.469-472
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• 1987

The hot-carrier induced degradation in very short-channel MOSFET was studied systematically. Under the traditional DC stress conditions, the threshold voltage shift (${\Delta}Vt$) and the transconductance degradation (${\Delta}Gm$/(Gmo-${\Delta}Gm$)) were confirmed to depend exponentially on the stress time and the dependency between the two parameters was proved to be linear. And the degradation due to the DC stress across gate and drain was studied. As the AC dynamic process is more realistic in actual device operation, the effects of dynamic stresses were studied.

• 한국정보기술응용학회:학술대회논문집
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• 한국정보기술응용학회 2002년도 추계공동학술대회 정보환경 변화에 따른 신정보기술 패러다임
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• pp.363-370
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• 2002

RF에서 동작하는 초미세 공정 MOS 트랜지스터의 기판 효과에 따른 기판회로망과 물리적 의미를 가지는 파라미터 추출법이 고려되었다. 제안된 기판 회로망에는 단일의 저항과 링 -형태의 기판 콘택에 의해 생성된 인덕터가 포함되었다 모델 파라미터는 최적화 과정없이 단절된 게이트와 공통-벌크 구성 을 갖는 MOS 트랜지스터에서 측정 된 S-파라미터로부터 추출된다. 제안된 기술은 다양한 크기 의 MOS 트랜지스터에 적용되어 졌다. 추출된 기 판 회 로망을 이 용한 가상실험 결과와 측정치는 약 30GHz까지 일치함을 검증하였다.

• 한국산업정보학회:학술대회논문집
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• 한국산업정보학회 2002년도 추계공동학술대회
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• pp.363-370
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• 2002

RF에서 동작하는 초미세 공정 MOS 트랜지스터의 기판 효과에 따른 기판 회로망과 물리적 의미를 가지는 파라미터 추출법이 고려되었다. 제안된 기판 회로망에는 단일의 저항과 링-형태의 기판 콘택에 의해 생성된 인덕터가 포함되었다. 모델 파라미터는 최적화 과정 없이 단절된 게이트와 공통-벌크 구성을 갖는 MOS 트랜지스터에서 측정된 S-파라미터로부터 추출된다. 제안된 기술은 다양한 크기의 MOS 트랜지스터에 적용되어졌다. 추출된 기판 회로망을 이용한 가상실험 결과와 측정치는 약 300Hz까지 일치함을 검증하였다.

• E2M - 전기 전자와 첨단 소재
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• 제7권3호
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• pp.225-230
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• 1994

In this paper, we have fabricated short channel MOSFETs with these parameters to verify the validity of process parameters extraction by DTC method. The experimental results of fabricated short channel devices according to the optimal process parameters demonstrate good device characteristics such as good drain current-voltage characteristics, low body effects and threshold voltage of$\leq$+-.1.0V, high punch through and breakdown voltage of$\leq$12V, low subthreshold swing(S.S) values of$\leq$105mV/decade.

• Transactions on Electrical and Electronic Materials
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• 제3권3호
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• pp.18-20
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• 2002

In sub-l/4 ${\mu}{\textrm}{m}$ NMOSFET with STI (Shallow Trench Isolation), the anomalous hump phenomenon of subthreshold region, due to capped p-TEOS/SiN induced defect, is reported. The hump effect was significantly observed as channel length is reduced, which is completely different from previous reports. Channel boron dopant redistribution due to the defect should be considered to improve hump characteristics besides considerations of STI comer and recess. 130

• 전자공학회논문지D
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• 제36D권5호
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• pp.21-28
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• 1999

Deep Submicron 영역에서 요구되는 고성능 소자로서 자기-정렬된 ESD(Elevated Source/Drain)구조의 MOSFET을 제안하였다. 제안된 ESD 구조는 일반적인 LDD(Lightly-Doped Drain)구조와는 달리 한번의 소오스/드레인 이온주입 과정이 필요하며, 건식 식각 방법을 적용하여 채널의 함몰 깊이를 조정할 수 있는 구조를 갖는다. 또한 제거가 가능한 질화막 측벽을 최종 질화막 측벽의 형성 이전에 선택적인 채널 이온주입을 위한 마스크로 활용하여 hot-carrier 현상을 감소시켰으며, 반전된 질화막 측벽을 사용하여 기존이 ESD 구조에서 문제시될 수 있는 자기-정렬의 문제를 해결하였다. 시뮬레이션 결과, 채널의 함몰 깊이 및 측벽의 넓이를 조정함으로써 충격이온화율(ⅠSUB/ID) 및 DIBL(Drain Induced Barrier Lowering) 현상을 효과적으로 감소시킬 수 있고, 유효채널 길이에 따라 차이가 있으나 두 번의 질화막 측벽을 사용함으로써 hot-carrier 현상이 개선될 수 있음을 확인하였다.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제51권3호
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• pp.134-140
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• 2002

Deep submicron NMOSFETs with elevated source/drain can be fabricated using self-aligned selective epitaxial growth(SEG) of silicon for enhanced device characteristics with shallow junction compared to conventional MOSFETs. Shallow junctions, especially with the heartily-doped S/D residing in the elevated layer, give hotter immunity to Yt roll off, drain-induced-barrier-lowering (DIBL), subthreshold swing (SS), punch-through, and hot carrier effects. In this paper, the characteristics of both deep submicron elevated source/drain NMOSFETs and conventional NMOSFETs were investigated by using TSUPREM-4 and MEDICI simulators, and then the results were compared. It was observed from the simulation results that deep submicron elevated S/D NMOSFETs having shallower junction depth resulted in reduced short channel effects, such as DIBL, SS, and hot carrier effects than conventional NMOSFETs. The saturation current, Idsat, of the elevated S/D NMOSFETs was higher than conventional NMOSFETs with identical device dimensions due to smaller sheet resistance in source/drain regions. However, the gate-to-drain capacitance increased in the elevated S/D MOSFETs compared with the conventional NMOSFETs because of increasing overlap area. Therefore, it is concluded that elevated S/D MOSFETs may result in better device characteristics including current drivability than conventional NMOSFETs, but there exists trade-off between device characteristics and fate-to-drain capacitance.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 추계학술대회 논문집 Vol.17
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• pp.207-209
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• 2004

Currently, for satisfying the needs of scaled MOSFET's a high quality thin oxide dielectric is desired because the properties of conventional $SiO_2$ film are not acceptable for these very small sized transistors. As an alternative gate dielectric have drawn considerable alternation due to their superior performance and reliability properties over conventional $SiO_2$, to obtain the superior characteristics of ultra thin dielectric films, $N_2O$ grown thin oxynitride has been proposed as a dielectric growtuanneal ambient. In this study the authors observed process characteristics of $N_2O$ grown thin dielectric. In view points of the process characteristics of MOS capacitor, the sheet resistance of 4.07$[\Omega/sq.]$, the film stress of $1.009e^{10}[dyne/cm^2]$, the threshold voltage$(V_t)$ of 0.39[V], the breakdown voltage(BV[V]) of 11.45[V] was measured in PMOS. I could achieve improved electrical characteristics and reliability for deep submicron MOSFET devices with $N_2O$ thin oxide.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권6호
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• pp.653-657
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• 2015

A new paired gate-source voltage RF capacitance-voltage (C-V) method of extracting the effective channel length and parasitic capacitance using the intersection between two closely spaced linear regression lines of the gate capacitance versus gate length measured from S-parameters is proposed to remove errors from conventional C-V methods. Physically verified results are obtained at the gate-source voltage range where the slope of the gate capacitance versus gate-source voltage is maximized in the inversion region. The accuracy of this method is demonstrated by finding extracted value corresponding to the metallurgical channel length.