• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.30A no.11
• /
• pp.122-131
• /
• 1993

In this paper, we have developed a submicron Si MOSFET simulator, which is physically based on the hydrodynamic energy transport mode. The simulator was used to investigate the nonstationary transport effects and the transient phenomena in submicron Si MOSFET's. It is found that the velocity overshoot and the carrier heating are dominant transport mechanism near the drain end of the channel and the transient phenomena is more retained in a long channel MOSFET.

• Electrical & Electronic Materials
• /
• v.8 no.3
• /
• pp.357-361
• /
• 1995

An experiment on characteristics of nMOSFET's in the long stress condition with the maximum of the substrate current has been carried out in order to study on the degradation due to the hot-carrier effect. Based on the measured result of the threshold voltage, the damage is mostly due to the hole injection into the oxide. After long stress, it was shown that the drain current increased at low gate voltages and hence decreased at high gate voltages.

• Electrical & Electronic Materials
• /
• v.6 no.1
• /
• pp.40-49
• /
• 1993

본 논문은 fitting 파라미커를 배제하고 2차원적 Poisson 방식을 도출해서 Submicron MOSFET의 model식을 완전히 해석적으로 성립시켰다. 이로 인해 포화영역, 문턱전압, 강반전에 대한 것이 동시에 표현되는 정확한 드레인 전류가 유도되었다. 더욱이 이 model은 short-channel과 body효과, DIBL효과, 그리고 carrier운동에 대한 것도 설명할 수 있으며 온도와 n$^{+}$접합, 산화층에 관련되는 문턱전압도 표현할 수 있었다.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.10
• /
• pp.62-66
• /
• 2011

In this study, a new RF method to extract the drain-source voltage Vds-dependent gate-bulk capacitance of deep-submicron MOSFETs is developed by determining Vds-independent gate-source overlap capacitance using measured S-parameters. The accuracy of extraction method is verified by observing good agreements between the measured and modeled S-parameters. The lateral channel doping profile in the drain region is experimentally measured using a Vds-dependent curve of the overlap and depletion length obtained from the extracted data.

• Proceedings of the KIEE Conference
• /
• 2002.07d
• /
• pp.2643-2645
• /
• 2002

집적회로에서 MOSFET이 낮은 Turn-on 저항이 요구되는 스위치 등으로 사용되는 경우 단일 MOSFET이 그 주변의 복잡한 기능의 회고보다 오히려 반도체 위에서 차지하는 면적이 막대하여 IC의 소형화 및 가격 경쟁력을 높이는데 있어서 중요한 문제로 대두되고 있다. Turn-on 시 극히 낮은 저항을 갖는 넓은 채널 폭(W)의 MOSFET을 submicron 공정에서 면적 면에서 효율적으로 설계하는 다양한 새로운 배치설계법을 소개하고, 이론 이용할 경우 기존의 구조에 비하여 약40%까지 면적을 절약할 수 있음을 보인다.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.30A no.12
• /
• pp.60-68
• /
• 1993

Thw VLSI device of submicron level trends to have a low level of reliability because of hot carriers which are caused by short channel effects and which do not appear in a long-channel MOSFET operated in 5V. In order to minimize the generation of hot carrier, much research has been made into various types of drain structures. This study has suggested CG MOSFET (Concaved Gate MOSFET) as new drain structure and compared its electrical characteristics with those of the conventional MOSFET and LDD-structured MOSFET by making use of a simulation method. These three device were assumed to be produced by the LOCOS process and a computer-based analysis(PISCES-2B simulator) was carried out to verify the hot electron-resistant behaviours of the devices. In the present simulation, the channel length of these devises was 1.0$\mu$m and their DC characteristics, such as VS1DT-IS1DT curves, gate and substrate current, potential contours, breakdown voltage and electric field were compared with one another.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1994.11a
• /
• pp.210-215
• /
• 1994

In the CMOS device, Counter doping is needed to adjust threshold voltage because of the difference between n-MOSFET and p-MOSFET well doping concentration when n+ polysilicon gate is used. Therefore buried channel is formed in the p-channel MOSFET degrading properties. So well doping concentration and doping condition should be considered in fabrication process and device design. Here we are to extract the initial process condition using simulation and fabricate p-MOSFET device and then compare the subthreshold characteristics of simulated and fabricated device.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.12
• /
• pp.27-34
• /
• 2004

The study on the RF substrate circuit is necessary to model RF output characteristics of deep submicron MOSFETs below 0.2$\mum$ gate length that have bun commercialized by the recent development of Si submicron process. In this paper, direct extraction methods are developed to apply for a simple substrate resistance model as well as another substrate model with connecting resistance and capacitance in parallel. Using these extraction methods, better agreement with measured Y22-parameter up to 30 GHz is achieved for 0.15$\mum$ CMOS device by using the parallel RC substrate model rather than the simple resistance one, demonstrating the RF accuracy of the parallel model and extraction technique. Using this model, bias and gate length dependent curves of substrate parameters in the RF region are obtained by increasing drain voltage of 0 to 1.2V at deep submicron devices with various gate lengths of 0.11 to 0.5㎛ These new extraction data will greatly contribute to developing a scalable RF nonlinear substrate model.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.13 no.12
• /
• pp.2655-2661
• /
• 2009

In this paper, an accurate noise parameters for thermal noise modeling of short channel MOSFET is derived and extracted. Fukui model for calculating the noise parameters of a MOSFET is modified by considering effects of parasitic elements in short channel, and it is compared with conventional noise model equation. In addition, for obtaining the intrinsic noise sources of devices, noise parameters(minimum noise figure $F_{min}$, equivalent noise resistance $R_n$ optimized source admittance $Y_{opt}=G_{opt}+B_{opt}$) in submicron MOSFETs is extracted. With this extraction method, the intrinsic noise parameters of MOSFET without effects of probe pad and extrinsic parasitic elements from RF noise measurements can be directly obtained.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1996.11a
• /
• pp.113-116
• /
• 1996

The drain current of the MOSFET in the off state(i.e., Id when Vgs=0V) is undesired but nevertheless important leakage current device parameter in many digital CMOS IC applications (including DRAMs, SRAMs, dynamic logic circuits, and portable systems). The standby power consumed by devices in the off state have added to the total power consumed by the IC, increasing heat dissipation problems in the chip. In this paper, hot-carrier-induced degra- dation and gate-induced-drain-leakage curr- ent under worse case in P-MOSFET\`s have been studied. First of all, the degradation of gate-induced- drain-leakage current due to electron/hole trapping and surface electric field in off state MOSFET\`s which has appeared as an additional constraint in scaling down p-MOSFET\`s. The GIDL current in p-MOSFET\`s was decreased by hot-electron stressing, because the trapped charge were decreased surface-electric-field. But the GIDL current in n-MOS77T\`s under worse case was increased.