• 한국항해항만학회지
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• 제48권2호
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• pp.88-96
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• 2024

This study examined challenges posed by two ferry routes, namely, Likoni and Mtongwe crossings, in the Mombasa Channel and their impact on navigational safety. Utilizing the Environmental Stress (ES) model, this study analyzed current ship traffic and assessed stress levels imposed by ferry crossing traffic on navigators. ES values revealed significant stress at these ferry crossings attributed to varying transit speeds. Standardizing transit speeds at two ferry passages can reduce high stress levels, presenting a viable solution. Furthermore, the IWRAP Mk2 simulation underscores crossing collisions as a significant concern, particularly at Likoni and Mtongwe crossings, due to increased ferry traffic. This research offers valuable insights for stakeholders, such as the Kenya Ports Authority (KPA), to develop targeted safety measures and enhance the flow of ship traffic in the channel.

• 한국전기전자재료학회논문지
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• 제14권11호
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• pp.869-873
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• 2001

The effects of alternate bias stress on p-channel poly-Si TFT\`s has been systematically investigated. We alternately applied positive and negative bias stress on p-channel poly-Si TFT\`s, device Performance(V$\_$th/, g$\_$m/, leakage current, S-slope) are alternately appeared to be increasing and decreasing. It has been shown that device performance degrade under the negative bias stress while improve under the positive bias stress. This effects have been related to the hot carrier injection into the gate oxide rather than the generation of defect states within the poly-Si/SiO$_2$ interface under alternate bias stress.

• 전자공학회논문지A
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• 제31A권8호
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• pp.72-79
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• 1994

In this paper semi empirical models are presented for the hot electron induced threshold voltage shift(${\Delta}V_{t}$) and effective channel shortening length (${\Delta}L_{H}$) in degraded PMOSFET. Trapped electron charges in gate oxide are calculated from the well known gate current model and ΔLS1HT is calculated by using trapped electron charges. (${\Delta}L_{H}$) is a function of gate stress voltage such as threshold voltage shift and degradation of drain current. From the correlation between (${\Delta}L_{H}$) has a logarithmic function of stress time. From the measured results, (${\Delta}V_{t}$) and (${\Delta}L_{H}$) are function of initial gate current and device channel length.

• 대한전자공학회논문지SD
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• 제37권4호
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• pp.31-37
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• 2000

금속 유도 측면 결정화 (Metal-Induced Lateral Crystallization; MILC)에 의해 저온다결정 실리콘 박막트랜지스터를 형성할 때 Ni박막을 게이트와 소오스/드레인간 경계로부터 거리를 달리하여 형성한 뒤 결정화시킴으로써 소오스와 드레인으로부터 결정화가 진행되어 서로 만나는 경계 면을 채널 내부 외부에 인위적으로 위치시킬 수 있었고 이들의 전기적 특성비교를 통하여 MILC경계가 트랜지스터 특성에 미치는 영향을 고찰할 수 있었다. MILC 경계를 채널 내부로부터 제거시킴으로써 On Current, Subthreshold slope 특성을 향상시킬 수 있었고 누설전류 특성도 크게 향상시킬 수 있었다. 채널 내부에 MILC 경계가 존재할 경우 전기적 스트레스를 인가함에 따라 누설전류의 양이 감소하였고, 전체 감소량은 채널 폭이 넓을수록 증가하였고 채널길이에는 무관하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2007년도 하계종합학술대회 논문집
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• pp.475-476
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• 2007

The stress induced leakage currents will affect data retention in synapse transistors and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses. The synapse transistor made by thin silicon oxides has represented the neural states and the manipulation which gaves unipolar weights. The weight value of synapse transistor was caused by the bias conditions. Excitatory state and inhibitory state according to weighted values affected the channel current. The stress induced leakage currents affected excitatory state and inhibitory state.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권1호
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• pp.94-100
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• 2017

Stress drain bias dependent current model is proposed for sub-70-nm p-channel metal-oxide semiconductor field-effect transistors (pMOSFETs) under drain-avalanche-hot-carrier (DAHC-) mechanism. The proposed model describes the both on-current and off-current degradation by using two device parameters: channel length variation (${\Delta}L_{ch}$) and threshold voltage shift (${\Delta}V_{th}$). Also, it is a simple and effective model of predicting reliable circuit operation and standby power consumption.

• 대한전자공학회논문지SD
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• 제45권4호
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• pp.57-63
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• 2008

본 논문에서는 Contact Etch Stop Layer (CESL)인 nitride film의 mechanical stress에 의해 인가되는 channel stress가 소자 특성에 미치는 영향에 대해 분석하였다. 잘 알려진 바와 같이 NMOS는 tensile stress와 PMOS에서는 compressive stress가 인가되었을 경우 drain current가 증가하였으며 그 원인을 체계적으로 분석하였다. NMOS의 경우 tensile stress가 인가됨으로써 back scattering ratio ($\tau_{sat}$)의 감소와 thermal injection velocity ($V_{inj}$)의 증가로 인해 mobility가 개선됨을 확인하였다. 또한 $\tau_{sat}$, 의 감소는 온도에 따른 mobility의 감소율이 작고, 그에 따른 mean free path ($\lambda_O$)의 감소율이 작기 때문인 것으로 확인되었다. 한편 PMOS의 compressive stress 경우에는 tensile stress에 비해 온도에 따른 mobility의 감소율이 크기 때문에 channel back scattering 현상은 심해지지만 source에서의 $V_{inj}$가 큰 폭으로 증가함으로써 mobility가 개선됨을 확인 할 수 있었다. 따라서 CES-Layer에 의해 인가된 channel stress에 따른 소자 특성의 변화는 inversion layer에서의 channel back scattering 현상과 source에서의 thermal injection velocity에 매우 의존함을 알 수 있다.

• 전자공학회논문지A
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• 제30A권12호
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• pp.77-87
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• 1993

PMOSFETs were studied on the effect of Hot-Carrier induced drain leakage current (Gate-Induced-Drain-Leakage). The result turned out that change in Vgl(drain voltage where 1pA/$\mu$m of drain leadage current flows) was largest in the Channel-Hot-Hole(CHH) injection condition and next was in dynamic stress and was smallest in electron trapping (Igmax) condition under various stress conditions. It was analyzed that if electron trapping occurrs in the overlap region of gate and drain(G/D), it reduces GIDL current due to increment of flat-band voltage(Vfb) and if CHH is injected, interface states(Nit) were generated and it increases GIDL current due to band-to-defect-tunneling(BTDT). Especially, under dynamic stress it was confirmed that increase in GIDL current will be high when electron injection was small and CHH injection was large. Therefore as applying to real circuit, low drain voltage GIDL(BTDT) was enhaced as large as CHH Region under various operating voltage, and it will affect the reliablity of the circuit.

• KEPCO Journal on Electric Power and Energy
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• 제2권2호
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• pp.223-225
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• 2016

The newly proposed analysis method using a direct-current current-voltage (DCIV) simulation is introduced for investigating leakage current composing MOS transistor. From comparing the density and location of traps using DCIV method and investigating the leakage current of gate channel transistor, we proposed the graphical analysis method to correlate the DCIV current and leakage mechanism by the traps. And, our graphical method intuitively explains that leakage current in MOS transistor is well correlated with the DCIV current of the MOS transistor arrays due to two kinds of traps created by Fowler-Nordheim (F-N) stress and Hot carrier stress, respectively.

• 한국전기전자재료학회논문지
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• 제13권9호
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• pp.729-734
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• 2000

Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. Different from using normal LOCOS technology deep-submicron CMOS devices using novel Shallow Trench Isolation(STI) technology have a unique"inverse narrow-channel effects"-when the channel width of the devices is scaled down, their threshold voltage is shrunk instead of increased as for the contribution of the channel edge current to the total channel current as the channel width is reduced. Secondly, Titanium silicide process clarified that fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel Two-step Deposited silicide(TDS) process has been developed. The key point of this process is the deposition and subsequent removal of titanium before silicidation. Based on the research, It is found that novel STI structure by the SEM, in addition to thermally stable silicide process was achieved. We also obtained the decrease threshold voltage value of the channel edge. resulting in the better improvement of the narrow channel effect. low sheet resistance and stress, and high threshold voltage. Besides, sheet resistance and stress value, rms(root mean square) by AFM were observed. On the electrical characteristics, low leakage current and trap density at the Si/SiO$_2$were confirmed by the high threshold voltage sub 0.1${\mu}{\textrm}{m}$ gate oxide.