• Proceedings of the KIPE Conference
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• 2014.07a
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• pp.159-160
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• 2014

기존 인터리브드 방식의 2상 이중 강압형 직류-직류 컨버터는 비절연 강압형 직류-직류 컨버터로 출력 전류 리플 감소, 이중 강압으로 인한 스위치 전압 스트레스 감소, 인덕터 전류 불평형 문제 해결, 그리고 스위칭 손실 감소 등의 장점으로 대용량 직류-직류 컨버터에 적합하다. 본 논문에서는 기존의 2상 이중 강압형 직류-직류 컨버터에 결합 인덕터를 적용하여 인덕터의 전류 리플을 감소시키고 이를 수치적으로 해석한다. 또한 결합 인덕터의 문제점인 각 상의 인덕터 전류 불평형으로 인한 인덕터 포화현상에 대하여 실험을 통해 확인 한다.

• Journal of Power Electronics
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• v.19 no.6
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• pp.1449-1457
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• 2019

This paper presents two voltage domain stacking topologies for powering integrated digital loads such as multiprocessors or 3D integrated circuits. Pairs of loads and capacitors are connected in series to form a stack of voltage domains. The voltage is balanced by switching the position of the capacitors in one case and the position of the loads in the other case. This method makes the voltage regulation robust to large differential load power consumption. The first configuration can be named the load stacking topology. The second configuration can be named the capacitor stacking topology. This paper aims at proposing and comparing these two topologies. Models of both topologies and a switching scheme are presented. The behavior, control scheme, losses and overall performance are analyzed and compared theoretically in simulation and experiments. Experimental results show that the capacitor stacking topology has better performance with a 30% voltage ripple reduction.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.1-7
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• 2008

This paper proposes 3.3V input and 1.8V output voltage mode step-down DC-DC buck converter for wireless mobile system which is designed in a standard 0.35$\mu$m CMOS process. The proposed capacitor multiplier method can minimize error amplifier compensation block size by 30%. It allows the compensation block of DC-DC converter be easily integrated on a chip. Also, we improve efficiency to 3% using low power buffer. Measurement result shows that the circuit has less than 1.17% output ripple voltage and maximum 83.9% power efficiency.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.5
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• pp.587-592
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• 2018

Because the brightness of an AMOLED is determined by the flowing current, each pixel of AMOLED operates via A current driving method. Therefore, it is necessary to supply power to adjust the amount of current according to THE user's requirement for AMOLED driving. In this study, an IP driver block was designed and a simulation was conducted for an AMOLED display, which supplies power as selected by users. The IP driver design focused on regulating the output power due to the OLED characteristics for the diode electric current according to the voltage to be activated by pulse-skipping mode (PSM) under low loads, and 1.5 MHz pulse-width modulation (PWM) for medium/high loads. The IP driver was designed to eliminate the ringing effects appearing from the dis-continue mode (DCM) of the step-up converter. The ringing effects destroy the power switch within the IC, or increase the EMI to the surrounding elements. The IP driver design minimized this through a ringing killer circuit. Mobile applications were considered to enable true shut-down capability by designing the standby current to fall below $1{\mu}A$ to disable it. The driver proposed in this paper can be applied effectively to the same system as the AMOLED display dual power management circuit.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.932_933
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• 2009

A technology based on thyristors will be used to manufacture the super-conducting coil AC/DC converters because of the low ratio of cost over installed power compared to a design based on GTO or similar technology. But phase-controlled converter suffers from fundamental disadvantage. They inject current harmonics into the input ac mains due to their nonlinear characteristics, thereby distort the supply voltage waveform, and demand reactive power from the associated ac power system at retarded angles. To overcome this disadvantage, in the case of two series converters at the DC side, connected to the same step-down transformer, apply for the sequence control. It is the most simple and efficient way to reduce the reactive power consumption at low cost. Analytical sequence control algorithm is suggested, the validity of the proposed scheme has been verified by experimental results with the small-scaled International Thermonuclear Experimental Reactor (ITER) Power Supply to minimize reactive power consumption.

• Journal of Power Electronics
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• v.9 no.2
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• pp.133-145
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• 2009

In this paper a modular high performance MV-to-LV rectifier based on a cascaded H-bridge rectifier is presented. The proposed rectifier can directly connect to the medium voltage levels and provide a low-voltage and highly-stable DC interface with the consumer applications. The input stage eliminates the necessity for heavy and bulky step-down transformers. It corrects the input power factor and maintains the voltage balance among the individual DC buses. The second stage includes the high frequency parallel-output DC/DC converters which prepares the galvanic isolation, regulates the output voltage, and attenuates the low frequency voltage ripple ($2f_{line}$) generated by the first stage. The parallel-output converters can work in interleaving mode and the active load-current sharing technique is utilized to balance the load power among them. The detailed analysis for modeling and control of the proposed structure is presented. The validity and performance of the proposed topology is verified by simulation and experimental results.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.9
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• pp.21-26
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• 2016

This paper presents a step-down DC-DC buck converter with a CCM/DCM dual-mode function for the internal power stage of portable electronic device. The proposed converter that is operated with a high frequency of 1 MHz consists of a power stage and a control block. The power stage has a power MOS transistor, inductor, capacitor, and feedback resistors for the control loop. The control part has a pulse width modulation (PWM) block, error amplifier, ramp generator, and oscillator. In this paper, an external capacitor for compensation has been replaced with a multiplier equivalent CMOS circuit for area reduction of integrated circuits. In addition, the circuit includes protection block, such as over voltage protection (OVP), under voltage lock out (UVLO), and thermal shutdown (TSD) block. The proposed circuit was designed and verified using a $0.18{\mu}m$ CMOS process parameter by Cadence Spectra circuit design program. The SPICE simulation results showed a peak efficiency of 94.8 %, a ripple voltage of 3.29 mV ripple, and a 1.8 V output voltage with supply voltages ranging from 2.7 to 3.3 V.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.7
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• pp.655-661
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• 2006

Dielectric and piezoelectric properties of PMN-PZT ceramics with a high mechanical quality factor$(Q_m)$ and a low temperature sintering temperature were investigated as a function of PZN substitution in order to develop multilayer piezoelectric transformer for AC-DC converter. Multilayer piezoelectric transformers were subsequently manufactured using the PMN-PZN-PZT ceramic offering the optimal behavior and then the electrical performance were invetigated. At the sintering temperature of $940^{\circ}C$, density, electromechanical coupling factor$(k_p)$, mechanical qualify factor$(Q_m)$ and dielectric constant$(\varepsilon_r)$ of 8 mol% PZN substituted specimen were $7.73g/cm^3$, 0.524, 1573 and 1455, respectively. The PZN substitution caused a increase in the dielectric constant and the electromechnical coupling factor. The voltage step-up ratio of multilayer piezoelectric transformer showed the maximum value at near the resonant frequency of 76.55 kHz and increased according to the increase of load resistance. The multilayer piezoelectric transformer with the output impedance coincided with the load resistance showed the temperature increase of less than $20^{\circ}C$ at the output power of 10 W. Based on the results, the manufactured multilayer transformer using the low temperature sintered PMN-PZN-PZT ceramics can be stably driven for both step-up and down transformers.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.9
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• pp.182-189
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• 2014

A tapped delay line time-to-digital converter (TDC) can be easily implemented using internal carry chains in a field-programmable gate array, and hence, its use is widespread. However, the tapped delay line TDC suffers from performance degradation because of differences in the delay times of dedicated carry chains. In this paper, a dual edge measurement method is proposed instead of a typical step signal to the delay cell to compensate for the performance degradation caused by wide-delay cells in carry chains. By applying a pulse of a fixed width as an input to the carry chains and using the time information between the up and down edges of the signal pulse, the timing accuracy can be increased. Two dedicated carry chain sites are required for the dual edge measurements. By adopting the proposed dual edge measurement method, the average delay widths of the two carry chains were improved by more than 35%, from 17.3 ps and 16.7 ps to 11.2 ps and 10.1 ps, respectively. In addition, the maximum delay times were improved from 41.4 ps and 42.1 ps to 20.1 ps and 20.8 ps, respectively.

• Journal of Navigation and Port Research
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• v.29 no.10 s.106
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• pp.859-863
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• 2005

This paper describes the improvement of power control characteristics of ship's emergency lighting power supply(SELPS), by which electric power is controlled extensively, and power ON-OFF is controlled and system parameter monitored in remote distance by PC serial communication. Proposed system is composed of step-down converter(SDC), emergency power supply circuit(EPSC), half bridge(HB) inverter, fluorescent lamp(FL) starting circuit, microprocessor control and multi communication circuit. Experimental works confirm that relative system stops when over current is detected and speedy and stable emergency power is supplied when main power source cut-off, and controls input power up to 35[$\%$] by adjusting pulse frequency of the HB inverter, and ON-OFF control of multiple SELS, real time transmission and monitor of parameters as to voltage, current, and power values are performed appropriately by PC communication.