• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.537-538
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• 2008

A step-down DC-DC converter with On-chip Compensation for battery-operated portable electronic devices which are designed in 0.18um CMOS standard process. In an effort to improve low load efficiency, this paper proposes the PFM (Pulse Frequency modulation) voltage mode 1MHz switching frequency step-down DC-DC converter with on-chip compensation. Capacitor multiplier method can minimize error amplifier compensation block size by 20%. It allows the compensation block of DC-DC converter be easily integrated on a chip and occupy less layout area. But capacitor multiplier operation reduces DC-DC converter efficiency. As a result, this converter shows maximum efficiency over 87% for the output voltage of 1.8V (input voltage : 3.3V), maximum load current 500mA, and 0.14% output ripple voltage. The total core chip area is $mm^2$.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.891-894
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• 2003

본 논문에서는 3-상 클럭을 이용하여 UP/DOWN 변환을 동시에 수행하는 DC/DC 변환기의 설계에 대해 설명한다. 기존의 UP/DOWN DC/DC 변환기의 경우에는 한 스텝당 변화하는 전압의 양이 많아서 출력에 수십 mV의 리플이 존재하게 된다. 이 리플을 줄이기 위해서는 L, C의 값을 크게 해 주어야하는 문제가 있다. 그러나, 설계된 UP/DOWN DC/DC 변환기는 기존의 UP/DOWN DC/DC 변환기의 구조를 가지면서, 3-상 클럭을 이용하여 한 스텝당 변화하는 전압의 양을 작게 하여 작은 L, C의 값을 가지고도 4mV이하의 출력 리플을 갖는 안정된 전압 변환을 하도록 설계하였다. 설계된 변환기는 0.25㎛ standard CMOS 공정을 이용하여 구현하였다. 구현 된 칩의 면적은 1.8 mm × 0.8 mm이다.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.11
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• pp.1622-1625
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• 2014

The main measurement uncertainty factors in DC high-voltage dividers for a national high-voltage standard are the measurement uncertainty of low-voltage arm and the stability of a high-voltage supply. In this study, the uncertainties by the two factors are greatly improved. As a result the measurement uncertainty for the DC high-voltage divider is reduced from $16{\times}10^{-6}(k=2)$ to $8{\times}10^{-6}(k=2)$ which is at international level.

• The Transactions of the Korean Institute of Power Electronics
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• v.6 no.6
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• pp.564-571
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• 2001

This paper presents the VLSI design of highly efficient low voltage DC/DC converter for portable devices. All active devices are integrated on a single chip using a standard 0.65$\mu\textrm{m}$ CMOS process. The converter operates at the switching frequency of 1MHz for reducing the size of passive elements and uses a ZVS for minimizing the switching loss at high frequency. Simulation results show that the circuit can achieve a 95% efficiency when the output voltage is controlled to be 2V with the load of lW.

• The Transactions of the Korean Institute of Power Electronics
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• v.17 no.6
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• pp.495-499
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• 2012

Recently, DC distribution systems become hot issues since DC type loads increase rapidly according to the expansion of IT equipment such as computers, servers, and digital devices; DC type loads will cover 50% for all electricity loads in 2020 which was mere 10% in 2000. DC distribution systems are also accelerated by the expansion of renewable power systems since they are easy to be interfaced with DC grids rather than AC grids. However, removing the fault current in DC grids is comparably difficult since the current in DC grids has non zero-crossing point like in AC grids. Thus, developing dedicated DC circuit breakers for DC grids is necessary to get safety for human and electrical facilities. Magnet arc extinguishing method is proper to small size DC circuit breakers. However, simple Magnet arc extinguishing method is not enough to break inductive fault currents. This paper proposed a novel DC circuit breaker against inductive fault current defined by IEEE C37.14-2004 Standard for Low-Voltage DC Power Circuit Breakers Used in Enclosures. The performance of the proposed DC circuit breaker was verified by an experimental circuit breaker test system built in this research.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.5B
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• pp.318-325
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• 2008

HomePlug AV(HPAV) is the standard for distribution of Audio/video content as well as data within the home by using the power line. It uses a hybrid access mechanism that combines TDMA with CSMA/CA for MAC technology. The CSMA/CA protocol in HPAV has two main control blobs that can be used for access control: contention window(CW) size and deferral counter(DC). In this paper, we extensively investigate the impacts of CW and DC on performance through simulations, and propose an adaptive mechanism that adjusts the CW size to enhance the throughput in HPAV MAC. We find that the CW size is more influential on performance than the DC. Therefore, to make controlling the network easier, our proposal uses a default value of DC and adjusts the CW size. Our scheme simply increases or decreases the CW size if the network is too busy or too idle, respectively, We compare the performance of our proposal with those of the standard and other competitive schemes in terms of throughput and fairness. Our simulation and analysis results show that our adaptive CW mechanism performs very well under various scenarios.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.599-600
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• 2008

This paper presents a high performance DC-DC boost converter by current-mode control method. As load current change, the converter change PWM/PFM operation automatically. current-mode DC-DC boost converter is implemented in a standard $0.35{\mu}m$ CMOS process. The peak efficiency was 94 % with a switching frequency of 1.2MHz.

• Proceedings of the IEEK Conference
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• 2002.06e
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• pp.207-210
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• 2002

This paper describes a design of multiple-mode single-output DC/DC converter which can be used in both up and down conversion. Proposed up/down converter does not produce a negative voltage which is generated in conventional buck-boost type converter. Three types of operation mode(up/down/bypass) are controlled by the input voltage sense and command signals of target output voltage. PFM(pulse frequency modulation) control is adopted and modified for fast tracking and for precise output voltage level with an aid of output voltage sense. Designed DC/DC converter has the performance of less than 5 % ripple and higher than 80 % efficiency. Chip area is 3.50 mm ${\times}$ 2.05 mm with standard 0.35 $\mu\textrm{m}$ CMOS technology.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.7A
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• pp.568-573
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• 2009

This paper presents a step-down DC-DC converter with On-chip Compensation for battery-operated portable electronic devices which are designed in O.13um CMOS standard process. In an effort to decrease system volume, this paper proposes the on chip compensation circuit using capacitor multiplier method. Capacitor multiplier method can minimize error amplifier's compensation capacitor size by 10%. It allows the compensation block of DC-DC converter be easily integrated on a chip and occupy less layout area. But capacitor multiplier operation reduces DC-DC converter efficiency. As a result, this converter shows maximum efficiency over 87.2% for the output voltage of 1.2V (input voltage : 3.3V), maximum load current 500mA, and 25mA output ripple current. This voltage mode controled buck converter has 1MHz switching frequency.

• Proceedings of the KIPE Conference
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• 2002.07a
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• pp.99-103
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• 2002

IEC 61800 is an international standard on adjustable speed electrical power drive systems, which consists of three parts. IEC 61800-1 and IEC 61800-2 apply to DC power drive systems and AC power drive systems, respectively, which include power conversion, control equipment, and also a motor or motors. IEC 61800-3 specifies EMC ( Electro Magnetic Compatibility ) requirements for adjustable speed AC or DC motor drives connected to main supplies up to AC 1,000 volts. This paper studies the standards related to EMC and the text summary of international standard IEC 61800-3 which is an EMC product standard including specific test methods.